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authorSimon Glass <sjg@chromium.org>2015-06-07 08:50:33 -0600
committerSimon Glass <sjg@chromium.org>2015-07-14 18:03:15 -0600
commit5d4a757ca5edb8782188c2bc2735f016e4b6c290 (patch)
tree703e4f08905083c82139ea0490cccb4c7f9c1dd6 /drivers
parenta7d0711a2486b7420a938831512d859879e613cb (diff)
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dm: spi: Correct minor nits in ICH driver
Tidy up three minor problems in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/ich.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 50354fd..6b6cfbf 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -422,7 +422,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
int using_cmd = 0;
int ret;
- /* Ee don't support writing partial bytes. */
+ /* We don't support writing partial bytes */
if (bitlen % 8) {
debug("ICH SPI: Accessing partial bytes not supported\n");
return -EPROTONOSUPPORT;
@@ -601,7 +601,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
return status;
if (status & SPIS_FCERR) {
- debug("ICH SPI: Data transaction error\n");
+ debug("ICH SPI: Data transaction error %x\n", status);
return -EIO;
}
@@ -619,7 +619,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
return 0;
}
-
/*
* This uses the SPI controller from the Intel Cougar Point and Panther Point
* PCH to write-protect portions of the SPI flash until reboot. The changes