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| * | spi: cadence_qspi: Fix CS timingsPhil Edworthy2016-12-15-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cadence QSPI controller has specified overheads for the various CS times that are in addition to those programmed in to the Device Delay register. The overheads are different for the delays. In addition, the existing code does not handle the case when the delay is less than a SCLK period. This change accurately calculates the additional delays in Ref clocks. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Remove returns from end of void functionsPhil Edworthy2016-12-15-8/+0
| | | | | | | | | | | | | | | | | | Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Use spi mode at the point it is neededPhil Edworthy2016-12-15-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | Instead of extracting mode settings and passing them as separate args to another function, just pass the SPI mode as an arg. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Clean up the #define namesPhil Edworthy2016-12-15-43/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of the #defines are for single bits in a register, where the name has _MASK on the end. Since this can be used for both a mask and the value, remove _MASK from them. Whilst doing so, also remove the unnecessary brackets around the constants. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Use #define for bits instead of bit shiftsPhil Edworthy2016-12-15-18/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the code already uses #defines for the bit value, rather than the shift required to get the value. This changes the remaining code over. Whislt at it, fix the names of the "Rd Data Capture" register defs. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Better debug information on the SPI clock ratePhil Edworthy2016-12-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Show what the output clock rate actually is. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Fix baud rate calculationPhil Edworthy2016-12-15-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the existing code, when the requested SPI clock rate is near to the lowest that can be achieved by the hardware (max divider of the ref clock is 32), the generated clock rate is wrong. For example, with a 50MHz ref clock, when asked for anything less than a 1.5MHz SPI clock, the code sets up the divider to generate 25MHz. This change fixes the calculation. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: cadence_qspi: Fix clearing of pol/pha bitsPhil Edworthy2016-12-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Or'ing together bit positions is clearly wrong. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | spi: Add error checking for invalid bus widthsSimon Glass2016-12-15-2/+2
| |/ | | | | | | | | | | | | | | | | | | At present an invalid bus width prints a message but does not return an error. This is the opposite of the correct behaviour. Adjust it to avoid code bloat in the common case, and avoid hard-to-debug failure in the uncommon case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | driver: fsl-mc: qbman: Add QBMAN 4.1 supportPriyanka Jain2016-12-15-13/+48
|/ | | | | | | | | | | | | | | LS2080A SoC family has QBMAN ver 4.0 whereas newer SoCs like LS2088A, LS1088A has QBMAN ver 4.1 QBMAN ver 4.0 and ver 4.1 supports dqrr size as 4 and 8 respectively. Add support of to check QBMAN version based on SoC SVR update dqrr_size accordingly update code to support larger dqrr_size Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-12-0/+226
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| * arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-12-0/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | spl: Add a name to the SPL load-image methodsSimon Glass2016-12-09-1/+1
|/ | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
* Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"Tom Rini2016-12-09-115/+17
| | | | | This reverts commit 3edc0c252257e4afed163a3a74aba24a5509b198, reversing changes made to bb135a0180c31fbd7456021fb9700b49bba7f533.
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-12-09-17/+115
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| * net: xilinx: Use mdio_register_seq() to support multiple instancesMichal Simek2016-12-08-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: Phani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
| * block: Move ceva driver to DMMichal Simek2016-12-08-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Series-to: sjg, agraf@suse.de Series-cc: uboot Series-version: 4 Series-changes: 2 - make ceva_init_sata static - Move SATA_CEVA to defconfig - Initalized max_lun and max_id platdata Series-changes: 3 - Extend Kconfig help description - sort dm.h - Remove SPL undefinition from board file - Fix Kconfig dependecies
| * dm: Add support for scsi/sata based devicesMichal Simek2016-12-08-9/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All sata based drivers are bind and corresponding block device is created. Based on this find_scsi_device() is able to get back block device based on scsi_curr_dev pointer. intr_scsi() is commented now but it can be replaced by calling find_scsi_device() and scsi_scan(). scsi_dev_desc[] is commented out but common/scsi.c heavily depends on it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol is reassigned to a block description allocated by uclass. There is only one block description by device now but it doesn't need to be correct when more devices are present. scsi_bind() ensures corresponding block device creation. uclass post_probe (scsi_post_probe()) is doing low level init. SCSI/SATA DM based drivers requires to have 64bit base address as the first entry in platform data structure to setup mmio_base. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Series-changes: 2 - Use CONFIG_DM_SCSI instead of mix of DM_SCSI and DM_SATA Ceva sata has never used sata commands that's why keep it in SCSI part only. - Separate scsi_scan() for DM_SCSI and do not change cmd/scsi.c - Extend platdata Series-changes: 3 - Fix scsi_scan return path - Fix header location uclass-internal.h - Add scsi_max_devs under !DM_SCSI - Add new header device-internal because of device_probe() - Redesign block device creation algorithm - Use device_unbind in error path - Create block device with id and lun numbers (lun was there in v2) - Cleanup dev_num initialization in block device description with fixing parameters in blk_create_devicef - Create new Kconfig menu for SATA/SCSI drivers - Extend description for DM_SCSI - Fix Kconfig dependencies - Fix kernel doc format in scsi_platdata - Fix ahci_init_one - vendor variable Series-changes: 4 - Fix Kconfig entry - Remove SPL ifdef around SCSI uclass - Clean ahci_print_info() ifdef logic
* | net/phy/vitesse: Rework RGMII skew configuration for VSC8601Alex2016-12-08-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | The VSC8601 config tried to add an RGMII skew based on #defines that no config defines. That's quite an ugly way to do it. Since the skew is only needed on RGMII interfaces, check the interface mode at runtime, and apply the settings accordingly. Tested on custom board with AM3352 SOC and VSC801 PHY. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: usb: r8152: Use ALLOC_CACHE_ALIGN_BUFFER() to allocate the buffersStefan Roese2016-12-08-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing on theadorable (Armada XP) has shown, that using this driver results in many cache misaligned warning, such as: CACHE: Misaligned operation at range [7fabd8fc, 7fabd900] This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the buffers on a cache aligned boundary. This fixes all warnings seen on the Armada XP platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ted Chen <tedchen@realtek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: fman: fix 2.5G SGMII settingsshaohui xie2016-12-08-10/+24
| | | | | | | | | | | | | | | | | | The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in set_if_mode(), and the serdes PCS configuration are wrong, this patch uses the correct settings took from Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: realtek: Only force master mode on rtl8211b/coliver@schinagl.nl2016-12-08-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY") added the define to force the PHY into master mode. Unfortunatly this is an all or nothing switch. So it applies to either all PHY's or no PHY's. The bug that define tried to solve was a buggy PLL in the RTL8211C only. The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was replaced with an RTL8211E. With this define however, both lime2 boards are either forced to master mode or not. We could of course have a binary for each board, but the following patch fixes this by adding a 'quirk' to the flags to the rtl8211b and rtl8211c only. It is now possible to force master mode, but only have it apply to the rtl8211b and rtl8211c. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: realtek: make define more consistentoliver@schinagl.nl2016-12-08-2/+2
| | | | | | | | | | | | | | | | All internal defines in the realtek phy are with a small X, except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: realtek: Use the BIT() macrooliver@schinagl.nl2016-12-08-2/+3
| | | | | | | | | | | | | | | | The BIT macro is the preferred method to set bits. This patch adds the bit macro and converts bit invocations. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: micrel: Fix error handlingMarek Vasut2016-12-08-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following error, the $ret variable handling must be part of the loop, while due to the missing parenthesis it was not. drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’: drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’: drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | usb: xhci-pci: Add DM supportStefan Roese2016-12-06-0/+81
|/ | | | | | | | | | | | | | | | | | This patch adds DM support to the xHCI PCI driver. Enabling its use e.g. in x86 platforms. Status: On the congatec BayTrail SoM, xHCI still does not work correctly with this patch. Some internal timeouts lead to resets (BUG). Additional work is needed here. I'm posting this version as WIP so that other developers interested in this support might use it as a start. I might get back to it in a few weeks as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-12-05-55/+155
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| * fsl/usb: enable the errata-a005697 for ls1012ajerry.huang@nxp.com2016-12-05-0/+4
| | | | | | | | | | | | | | Enable the errata-a005697 for ls1012a Signed-off-by: Changming Huang <jerry.huang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl/ddr: Add erratum_a009942_check_cpo and clean related erratumShengzhou Liu2016-12-05-31/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl/ddr: Fix compiling warningShengzhou Liu2016-12-05-32/+25
| | | | | | | | | | | | | | | | | | Fix following warning in case multiple erratum macro was not defined. warning: unused variable 'tmp' warning: unused variable 'ddr_freq' Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://www.denx.de/git/u-boot-i2cTom Rini2016-12-05-1128/+635
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| * dm: i2c: Add a note to I2C drivers which need conversionSimon Glass2016-12-05-0/+42
| | | | | | | | | | | | | | | | Maintainers need to be notified more directly of the need to convert these drivers. Add a note to the top each affected file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * samsung: i2c: Split the high-speed I2C code into a new driverSimon Glass2016-12-05-545/+591
| | | | | | | | | | | | | | | | | | Now that driver model is used for I2C on all boards, we can split the high-speed code into its own driver. There is virtually no common code, and this significantly reduces confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
| * samsung: i2c: Drop old code from I2C driverSimon Glass2016-12-05-583/+2
| | | | | | | | | | | | | | Now that all boards use DM_I2C we can drop the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* | sata: sata_mv: Fix misaligned cache warningsStefan Roese2016-12-05-3/+9
| | | | | | | | | | | | | | | | This patch fixes the warnings about misaligned cache on Armada XP: CACHE: Misaligned operation at range [7facb400, 7facb460] Signed-off-by: Stefan Roese <sr@denx.de>
* | pci: mvebu: Add PCIe driver for Armada-8KShadi Ammouri2016-12-05-0/+546
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core. The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support. Tested on the Marvell DB-88F8040 Armada-8K eval board. Signed-off-by: Shadi Ammouri <shadi@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* | drivers/phy: marvell: Add support for the slave CP COMPHY deviceStefan Roese2016-12-05-3/+14
|/ | | | | | | | | | | | | | | With the support for the Armada 8k, a 2nd COMPHY controller now needs to get supported from the CP110 slave controller. This patch adds support for this 2nd contoller in the COMPHY driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* usb: gadget: remove unused shortname variableAndre Przywara2016-12-04-1/+0
| | | | | | | | | | | The shortname variable isn't referenced anywhere in the code, so just remove it. Pointed out by a GCC 6.2 default warning option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: eth: r8152_fw: fix indentationAndre Przywara2016-12-04-4/+4
| | | | | | | | | | | Apparently the indentation is wrong here, fix this to avoid compiler warnings and puzzled readers. Pointed out by GCC 6.2's -Wmisleading-indentation warning. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* marvell: comphy_a3700: fix bitmaskAndre Przywara2016-12-04-2/+2
| | | | | | | | | | | | | Obviously the mask for the rx and tx select field cannot be right, as it would overlap in one and exceed the 32-bit register in the other case. From looking at the neighbouring bits it looks like the mask should be really 4 bits wide instead of 8. Pointed out by a GCC 6.2 (default) warning. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* net: rtl8169: remove unneeded definitionAndre Przywara2016-12-04-3/+0
| | | | | | | | The rtl8169_intr_mask variable isn't used anywhere in the code, so just remove it to avoid a GCC 6.2 compiler warning. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: e1000: fix indentationAndre Przywara2016-12-04-3/+2
| | | | | | | | | | | Apparently the indentation is off here, for the IGB model just want to bail out early. Fix this to avoid both compiler warnings and puzzled readers. Pointed out by GCC 6.2's -Wmisleading-indentation warning. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* mtd: cfi_flash: fix indentationAndre Przywara2016-12-04-2/+2
| | | | | | | | | | | | The indentation is misleading here and suggests that the write command will be only executed in the else clause. It seems like this is not intended, so fix the indentation to avoid both compiler warnings and puzzled readers. Pointed out by GCC 6.2's -Wmisleading-indentation warning. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefan Roese <sr@denx.de>
* serial: Drop the s3c24x0 serial driverSimon Glass2016-12-04-209/+0
| | | | | | | | This is not used by any boards. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: David Müller <d.mueller@elsoft.ch> Reviewed-by: Jagan Teki <jagan@openedev.com>
* ARM: OMAP4+: Add support for getting pbias info from boardLokesh Vutla2016-12-04-46/+22
| | | | | | | | | | | | | Palmas driver assumes it is always TPS659xx regulator on all DRA7xx based boards to enable mmc regulator. This is not true always like in case of DRA71x-evm. So get this information based on the board. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Delete omap4_vmmc_pbias_config from omap_hsmmc.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-dmTom Rini2016-12-03-89/+564
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| * cmd: crosec: Move cros_ec_decode_region helper to cmd/cros_ec.cMoritz Fischer2016-12-02-16/+0
| | | | | | | | | | | | | | | | | | | | | | The cros_ec_decode_region() function is only used in combination with the crosec cmds. Move the function to the correct place. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: u-boot@lists.denx.de Acked-by: Simon Glass <sjg@chromium.org>
| * drivers: usb: musb: add ti musb host driver with driver model supportMugunthan V N2016-12-02-0/+191
| | | | | | | | | | | | | | | | | | Add a TI MUSB host driver with driver model support and the driver will be bound by the MUSB wrapper driver based on the dr_mode device tree entry. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * drivers: usb: musb: adopt musb backend driver to driver modelMugunthan V N2016-12-02-11/+11
| | | | | | | | | | | | | | | | | | | | Currently all backend driver ops uses hard coded physical address, so to adopt the driver to DM, add device pointer to ops call backs so that drivers can get physical addresses from the usb driver priv/plat data. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * drivers: usb: musb: add ti musb misc driver for wrapperMugunthan V N2016-12-02-0/+74
| | | | | | | | | | | | | | | | Add a misc driver for MUSB wrapper, so that based on dr_mode the USB devices can bind to USB host or USB device drivers. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-10-31 05:24:40 +0000