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* board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-2/+0
| | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* dm: avoid dev->req_seq overflowRobert Baldyga2014-09-23-0/+2
| | | | | | | | | | | | | Since dev->req_seq value is initialized from "reg" property of fdt node, there is posibility, that address value contained in fdt is greater than INT_MAX, and then value in dev->req_seq is negative which led to probe() fail. This patch fix this problem by ensuring that req_seq is positive, unless it's one of errno codes. Signed-off-by: Robert Baldyga <r.baldyga@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: serial: Don't require device tree to configure a consoleSimon Glass2014-09-23-1/+2
| | | | | | Allow serial_find_console_or_panic() to work without a device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Allow device_bind() to used without CONFIG_OF_CONTROLSimon Glass2014-09-23-2/+5
| | | | | | | | The sequence number support in driver model requires device tree control. It should be skipped if CONFIG_OF_CONTROL is not defined, and should not require functions from fdtdec. Signed-off-by: Simon Glass <sjg@chromium.org>
* sf: Add an empty entry to the parameter listSimon Glass2014-09-23-0/+1
| | | | | | | | The list is supposed to be terminated with a NULL name, but is not. If a board probes a chip which does not appear in the table, U-Boot will crash (at least on sandbox). Signed-off-by: Simon Glass <sjg@chromium.org>
* mtd: atmel_nand: Disable subpage NAND write when using Atmel PMECCBoris BREZILLON2014-09-19-0/+1
| | | | | | | | | | | Disable subpage write when using PMECC to prevent buggy partial page write. This fix has been taken from linux sources (see commit 90445ff6241e2a13445310803e2efa606c61f276) Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* USB: ehci-atmel: use pcr to enable or disable clockBo Shen2014-09-19-0/+8
| | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* USB: ohci-at91: use pcr to enable or disable clockBo Shen2014-09-19-4/+4
| | | | | | | | If the SoC has pcr, we use pcr (peripheral control register) to enable or disable clock. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc registerWu, Josh2014-09-19-10/+14
| | | | | | | | | | We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access. But in the driver we also use the readl(b)/writel. To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-17-15/+107
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| * pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-4/+36
| | | | | | | | | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * arm: vf610: lpuart: disable FIFO on initializatonStefan Agner2014-09-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * arm: vf610: lpuart: fix status register handlingStefan Agner2014-09-09-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * pci: add support for board_pci_fixup_dev functionTim Harvey2014-09-09-0/+4
| | | | | | | | | | | | | | Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * sata: dwc_ahsata: implement sata_port_statusNikita Kiryanov2014-09-09-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata. Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam2014-09-09-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam2014-09-09-2/+10
| | | | | | | | | | | | | | | | | | | | | | mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* | net: usb: Add SMSC copyright to smsc95xx driverSimon Glass2014-09-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver was upstreamed without an SMSC copyright, even thought it seems that SMSC was the original author. See the kernel version for a code comparison: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=2f7ca802bdae2ca41022618391c70c2876d92190 It's not clear who actually moved this code, or whether the kernel was the original source, or somewhere else, but it probably should still have the SMSC copyright. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mtdcore: Fix a build error with CONFIG_CMD_MTDPARTS_SPREADmaxin.john@enea.com2014-09-16-2/+2
| | | | | | | | | | | | This patch fixes the build error for CONFIG_CMD_MTDPARTS_SPREAD Signed-off-by: Maxin B. John <maxin.john@enea.com>
* | mtd: nand: davinci_nand: update write_page function for keystone RBLKhoronzhuk, Ivan2014-09-16-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | After mtd was synced with Linux 3.14 (ff94bc40af3481d47546595ba73c136de6af6929) the number of parameters for write_page function of nand_chip was changed. The additional two var were needed for subpage write. As keystone has no supbage write they are not needed. So correct only function definition by upgrading it's parameter list. That helps to get ritd of compilation warning. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | kbuild: force to define __UBOOT__ in all the C sourcesMasahiro Yamada2014-09-16-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot has imported various source files from other projects, mostly Linux. Something like #ifdef __UBOOT__ [ modification for U-Boot ] #else [ original code ] #endif is an often used strategy for clarification of adjusted parts, that is, easier re-sync in future. Instead of defining __UBOOT__ in each source file, passing it from the top Makefile would be easier. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* | rtl8169: Defer network packet processingThierry Reding2014-09-16-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When network protocol errors occur (such as a file not being found on a TFTP server), the processing done by the NetReceive() function will end up calling the driver's .halt() implementation. However, after that the device no longer has access to the memory buffers and will cause errors such as this in the rtl_recv() function when trying to hand descriptors back to the device: pci_hose_bus_to_phys: invalid physical address This can be fixed by deferring processing of network packets until the descriptors have been handed back. That way rtl_halt() tearing down network buffers is not going to prevent access to the buffers. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | openrisc: Fix a few type cast related warningsVasili Galka2014-09-15-4/+4
| | | | | | | | | | | | | | | | | | | | | | Use size_t type for positive offsets instead of the loff_t type. The later is defined as long long, which is larger than the pointer type on OpenRISC architecture and therefore the following warning was generated: "warning: cast to pointer from integer of different size" Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2014-09-13-117/+838
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| * | dm: tegra: Enable driver model for serialSimon Glass2014-09-10-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use driver model for serial ports. Since Tegra now uses driver model for serial, adjust the definition of V_NS16550_CLK so that it is clear that this is only used for SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: serial: Add driver model support for ns16550Simon Glass2014-09-10-3/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: serial: Collect common baud rate code in ns16550Simon Glass2014-09-10-20/+13
| | | | | | | | | | | | | | | | | | | | | The same sequence is used in several places, so move it into a function. Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: serial: Move baud rate calculation to ns16550.cSimon Glass2014-09-10-11/+21
| | | | | | | | | | | | | | | | | | | | | Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: serial: Support a coloured consoleSimon Glass2014-09-10-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current sandbox serial driver is a pretty trivial example and does not have the featues that might be needed for other board serial drivers. To help provide a better example, add a text colour property to the device tree for sandbox. This uses platform data, a device tree node, driver private data and a remove() method. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Convert serial driver to use driver modelSimon Glass2014-09-10-31/+36
| | | | | | | | | | | | | | | | | | | | | Adjust the sandbox serial driver to use the new driver model uclass. The driver works much as before, but within the new framework. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Add a uclass for serial devicesSimon Glass2014-09-10-0/+217
| | | | | | | | | | | | | | | | | | | | | | | | Serial devices support simple byte input/output and a few operations to find out whether data is available. Add a basic uclass for serial devices to be used by drivers that are converted to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Adjust lists_bind_fdt() to return the bound deviceSimon Glass2014-09-10-4/+8
| | | | | | | | | | | | | | | | | | | | | Allow the caller to find out the device that was bound in response to this call. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | serial: Set up the 'priv' pointer when creating a serial deviceSimon Glass2014-09-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The stdio_dev structure has a private pointer for its creator, but it is not set up by the serial system. Set it to point to the serial device so that it can be found by code called by stdio. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | tegra: Convert tegra GPIO driver to use driver modelSimon Glass2014-09-10-55/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-12-57/+308
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| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-09-12/+270
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| | * video: Add driver for Parade PS8625 dP to LVDS bridgeVadim Bendebury2014-09-05-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization table comes from the "Illustration of I2C command for initialing PS8625" document supplied by Parade. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * video: exynos_fimd: Add framework to disable FIMD sysmmuAjay Kumar2014-09-05-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default. We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * exynos_fb: Remove usage of static definesAjay Kumar2014-09-05-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16. Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | mtd: nand: omap_gpmc: Fix 'bit-flip' errorsRostislav Lisovy2014-09-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly due to a NAND protocol violation in the omap driver since the Random Data Output command (05h-E0h) expects to see only the column address that should be addressed within the already loaded read page into the read buffer. Only 2 address cycles with ALE active should be provided between the 05h and E0h commands. The Page read command expects the full address footprint (2bytes for column address + 3bytes for row address), but once the page is loaded into the read buffer, Random Data Output should be used with only 2bytes for column address." This patch combines the solution proposed in the mailinglist and the patch provided by the Spansion company (GPLv2 code, source: http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip) Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
| * | mtd: nand: omap_gpmc: Enable multiple NAND flash devicesRostislav Lisovy2014-09-04-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the CS of a device connected to the GPMC was stored in the global variable, it was not possible to use multiple devices. In this patch the CS is stored per device in its 'struct omap_nand_info'. This makes it possible to use up to 'GPMC_MAX_CS' NAND Flash devices connected to U-boot. Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
| * | mtd: nand: davinci_nand: correct keystone RBL layout definitionKhoronzhuk, Ivan2014-09-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In case when 4K page keystone RBL layout is used the compilation error is appeared. That's because the #ifdef has to be placed under struct name. This patch correct it. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | keystone2: use readl/writel functions instead of redefinitionKhoronzhuk, Ivan2014-09-04-20/+15
| |/ | | | | | | | | | | | | | | There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com>
* | video: dcu: Add DCU driver supportWang Huan2014-09-08-0/+366
| | | | | | | | | | | | | | | | | | This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | serial: lpuart: add 32-bit registers lpuart supportJingchang Lu2014-09-08-0/+118
| | | | | | | | | | | | | | | | | | On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers are 32-bit. This patch adds the support for 32-bit registers on LS102xA. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
* | driver/ddr/fsl: Add support of overriding chip select write levelingYork Sun2014-09-08-0/+5
| | | | | | | | | | | | | | | | | | | | JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>
* | driver/ddr/freescale: Fix DDR3 driver for ARMYork Sun2014-09-08-1/+1
| | | | | | | | | | | | | | Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun <yorksun@freescale.com>
* | driver/ddr/freescale: Add support of accumulate ECCYork Sun2014-09-08-0/+5
| | | | | | | | | | | | | | | | | | If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun <yorksun@freescale.com>
* | ls102xa: esdhc: Add esdhc support for LS102xAWang Huan2014-09-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | For LS1, esdhc is big-endian IP. Accessing the registers should be in big-endian mode. So we use esdhc_read32() to read Host controller capabilities register for LS1. For LS1, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | ls102xa: etsec: Add etsec support for LS102xAAlison Wang2014-09-08-0/+7
| | | | | | | | | | | | | | | | | | This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
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