summaryrefslogtreecommitdiff
path: root/drivers
Commit message (Collapse)AuthorAgeLines
...
* | | dm: serial: Drop serial_max3100 serial driverSimon Glass2016-02-08-295/+0
| | | | | | | | | | | | | | | | | | | | | | | | This does not appear to be used, and has not been converted to driver model by the deadline (doc/driver-model/serial-howto.txt). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | dm: freescale: serial: Drop serial_imx serial driverSimon Glass2016-02-08-224/+0
| | | | | | | | | | | | | | | | | | | | | | | | This does not appear to be used, and has not been converted to driver model by the deadline (doc/driver-model/serial-howto.txt). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | dm: opencores: Drop opencores_yanu serial driverSimon Glass2016-02-08-243/+0
| | | | | | | | | | | | | | | | | | | | | | | | This does not appear to be used, and has not been converted to driver model by the deadline (doc/driver-model/serial-howto.txt). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | dm: freescale: Drop mxs_auart serial driverSimon Glass2016-02-08-152/+0
| | | | | | | | | | | | | | | | | | | | | This does not appear to be used, and has not been converted to driver model by the deadline (doc/driver-model/serial-howto.txt). Signed-off-by: Simon Glass <sjg@chromium.org>
* | | serial: serial_stm32: move clock config from driver to boardVikas Manocha2016-02-08-40/+0
| | | | | | | | | | | | | | | | | | | | | | | | This patch removes the uart clock enable from serial driver & move it in the board code. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2016-02-08-25/+27
|\ \ \
| * | | net: davinci_emac: fix NULL check after pointer dereferenceVishwas Srivastava2016-02-06-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NULL check is made after the pointer dereference. This patch fixes this issue. Signed-off-by: Vishwas Srivastava <vishu.kernel@gmail.com> CC: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | net: fix wrong initialization in davinci-emac driverVishwas Srivastava2016-02-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | emac module of the davinci platform supports only 8 tx and 8 rx channels (total 16). emac driver for davinci platform, however, while doing initialization of the dma descriptor head pointers, wrongly initializes the 16 head pointers (instead of 8) for tx dma and 16 head pointers (insted of 8) for rx dma, which is wrong. The result is, that this register initilization spills over the other registers which was not intended and is undesirable. This patch fixes this problem. Signed-off-by: Vishwas Srivastava <vishu.kernel@gmail.com> CC: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | video: Use 'int' for loop variables instead of shortSimon Glass2016-02-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using short doesn't save anything and is confusing when the width and height variables are ulong. This may fix Coverity CID134902 but I doubt it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | Use correct spelling of "U-Boot"Bin Meng2016-02-06-21/+21
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* | | net: e1000: Convert to use DM PCI APIBin Meng2016-02-05-1/+78
| | | | | | | | | | | | | | | | | | | | | Update this driver to use proper DM PCI APIs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | net: designware: Use dm_pci_mem_to_phys() in the probe routineBin Meng2016-02-05-3/+1
| | | | | | | | | | | | | | | | | | | | | Convert to use native DM PCI API dm_pci_mem_to_phys(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | net: pch_gbe: Convert to use DM PCI APIBin Meng2016-02-05-16/+13
| | | | | | | | | | | | | | | | | | | | | Use native DM PCI APIs instead of legacy compatible ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | x86: ich6_gpio: Convert to use proper DM APIBin Meng2016-02-05-102/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | x86: pch9: Implement get_io_base opBin Meng2016-02-05-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | IO_BASE is only seen on PCH9 device, implement the get_io_base op. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | dm: pch: Add get_io_base opBin Meng2016-02-05-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | x86: pch: Implement get_gpio_base opBin Meng2016-02-05-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | dm: pch: Add get_gpio_base opBin Meng2016-02-05-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | dm: pch: Rename get_sbase op to get_spi_baseBin Meng2016-02-05-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | dm: pch: Remove pch_get_version opBin Meng2016-02-05-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | spi: ich: Change PCHV_ to ICHV_Bin Meng2016-02-05-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ICH SPI controller supports two variants, one of which is ICH7 compatible and the other is ICH9 compatible. Change 'pch_version' to 'ich_version' to better match its original name. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | spi: ich: Use compatible strings to distinguish controller versionBin Meng2016-02-05-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
* | | spi: ich: Some clean upBin Meng2016-02-05-47/+47
|/ / | | | | | | | | | | | | | | | | | | | | | | This cleans up the ich spi driver a little bit: - Remove struct ich_spi_slave that is not referenced anywhere - Remove ending period in some comments - Move struct ich_spi_platdata and struct ich_spi_priv to ich.h - Add #ifndef _ICH_H_ .. in ich.h Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-02-04-2/+2
|\ \
| * | usb: gadget: dwc2_udc_otg: modified the check condition for max packet size ↵Frank Wang2016-02-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of ep_in in high speed In current high speed fastboot, fs_ep_in.wMaxPacketSize is configured 64 bytes as default, as a result, it failed to match the size at initialization stage in usb controller. Actually, hardware can support less than or equal to 512 bytes in high speed mode, so I changed the condition from '!=' to '>' to fix this issue. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Tested-by: Steve Rae <srae@broadcom.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-02-04-1/+1
|\ \ \ | |_|/ |/| |
| * | Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals"Dinh Nguyen2016-02-04-1/+1
| |/ | | | | | | | | | | | | | | Apparently, the logic for the FPGA global bit is not universal between Gen5 and Gen10 devices is not the same. Disabling this bit, while applicable to Gen10 devices, will break FPGA programming on Gen5 devices. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | dm: vybrid_gpio: Drop legacy codeBhuvanchandra DV2016-02-02-18/+0
| | | | | | | | | | | | | | | | All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: lpuart: Drop the legacy codeBhuvanchandra DV2016-02-02-99/+2
|/ | | | | | | | All boards using this driver are with device tree support, hence drop the legacy code in driver to have a pure DT solution. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-02-50/+82
|\
| * atmel_nand: Add 32 bit ecc support for sama5d2 chipJosh Wu2016-02-02-1/+9
| | | | | | | | | | | | | | | | | | | | Also if minimum ecc requirment is bigger then what we support, then just use our maxium pmecc support. But it is not safe, so we'll output a warning about this. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * atmel_nand_ecc: update pmecc registers according to sama5d2 chipJosh Wu2016-02-02-4/+32
| | | | | | | | | | | | | | | | | | | | 1. add the pmecc register mapping for sama5d2. 2. add the pmecc error location register mapping for sama5d2. 3. add some new field that is different from old ip. 4. add sama5d2 pmecc ip version number. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * atmel_nand: use the definition: PMECC_OOB_RESERVED_BYTES instead magic numberJosh Wu2016-01-27-1/+1
| | | | | | | | | | | | | | | | | | As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the PMECC_OOB_RESERVED_BYTES. So use it in the driver. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * atmel_nand: add '\n' in the end of error message for better displayJosh Wu2016-01-27-2/+2
| | | | | | | | | | | | | | | | Also align the open parenthesis. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * atmel_nand: use nand ecc_{strength, step}_ds instead of our own functionJosh Wu2016-01-27-37/+7
| | | | | | | | | | | | | | | | | | | | Since ecc_{strength,step}_ds is introduced in nand_chip structure for minimum ecc requirements. So we can use them directly and remove our own get_onfi_ecc_param function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * net: macb: Not all the GEM are gigabit capableGregory CLEMENT2016-01-27-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the initialization of PHY the gigabit bit capable is set if the controller is a GEM. However, for sama5d2 and sama5d4, the GEM is configured to support only 10/100. Improperly setting the GBE capability leads to an unresponsive MAC controller. This patch fixes this behavior allowing using the gmac with these SoCs. Suggested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * mmc: atmel: Properly fix clock configurationGregory CLEMENT2016-01-27-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timing issue occurs on eMMC not only when modifying the frequency but also for all the switch command(CMD6). According to the MMC spec waiting 8 clocks after a switch command would be the thing to do. This patch allows fixing CPU hang observed when trying to changing the bus width on a eMMC on SAMA5D4. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Marek Vasut <marex@denx.de> # on DENX MA5D4EV Acked-by: Marek Vasut <marex@denx.de> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> # on atngw100 Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-02-1/+2
|\ \
| * | driver: net: fsl-mc: Update print to reflect correct stringPrabhakar Kushwaha2016-02-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update printf with dpbp_exit to match with previous function call. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: net: fsl-mc: Memset dprc_cfg before configuringPrabhakar Kushwaha2016-02-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All fields of struct dprc_cfg are not being configured while creating child container. "Not" configured fields are assumed to be 0. So memset dprc_cfg before configuring the fields. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | drivers: net: Add ethernet driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+899
| | | | | | | | | | | | | | | | | | | | | | | | This driver implements MAC and MII layer of the ethernet controller. Network data transfer is handled by controller internal DMA engine. Ethernet controller is configurable through device-tree file. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | | drivers: net: phy: add SMSC LAN8740 Phy support.Purna Chandra Mandal2016-02-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add SMSC LAN8740 Phy support required for PIC32MZDA devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | drivers: mmc: add driver for Microchip PIC32 SDHCI controller.Andrei Pistirica2016-02-01-1/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements platform specific glue and fixups for PIC32 internal SDHCI controller. Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | drivers: serial: add driver for Microchip PIC32 UART controller.Paul Thacker2016-02-01-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds PIC32 UART controller support based on driver model. Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | drivers: gpio: add driver for Microchip PIC32 GPIO controller.Purna Chandra Mandal2016-02-01-1/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In PIC32 GPIO controller is part of PIC32 pin controller. PIC32 has ten independently programmable ports and each with multiple pins. Each of these pins can be configured and used as GPIO, provided they are not in use for other peripherals. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | drivers: pinctrl: Add pinctrl driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+374
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.Purna Chandra Mandal2016-02-01-0/+434
|/ / | | | | | | | | | | | | | | | | | | PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | video: sandbox: Allow selection of font size and console nameSimon Glass2016-01-30-0/+2
| | | | | | | | | | | | | | | | For testing it is useful to be able to select the font size and the console driver for sandbox. Add this information to platform data and copy it to the video device when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* | video: Allow selection of the driver and font sizeSimon Glass2016-01-30-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | Provide a way for the video console driver to be selected. This is controlled by the video driver's private data. This can be set up when the driver is probed so that it is ready for the video_post_probe() method. The font size is provided as well. The console driver may or may not support this depending on its capability. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Anatolij Gustschin <agust@denx.de>
generated by cgit v1.1 at 2024-11-01 06:34:37 +0000