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authorBin Meng <bmeng.cn@gmail.com>2016-02-01 01:40:45 -0800
committerBin Meng <bmeng.cn@gmail.com>2016-02-05 12:47:21 +0800
commit79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7 (patch)
tree10b2756494ba0b3d3a0967f1ef82380689612e51 /drivers
parentec2af6f82d4ee07fa19877e2bb2e5c80d8d6962b (diff)
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dm: pch: Add get_io_base op
On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pch/pch-uclass.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c
index 48a3965..7216660 100644
--- a/drivers/pch/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -44,6 +44,17 @@ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
return ops->get_gpio_base(dev, gbasep);
}
+int pch_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ *iobasep = 0;
+ if (!ops->get_io_base)
+ return -ENOSYS;
+
+ return ops->get_io_base(dev, iobasep);
+}
+
static int pch_uclass_post_bind(struct udevice *bus)
{
/*