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path: root/drivers/spi/mxc_spi.c
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* IMX: uniform GPIO interface using GPIO frameworkStefano Babic2011-09-04-4/+4
| | | | | | | | | IMX processors has a slightly different interface to access GPIOs and do not make use of the provided GPIO framework. The patch substitutes mxc_ specific functions and make use of the API in asm/gpio.h Signed-off-by: Stefano Babic <sbabic@denx.de>
* MX31: Cleanup clock functionStefano Babic2011-07-18-2/+0
| | | | | | | The patch provide the same API used with other i.MX processors and get rid of mx31_ functions. Signed-off-by: Stefano Babic <sbabic@denx.de>
* mxc_spi.c: typo fixedHelmut Raiger2011-06-21-1/+1
| | | | Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
* IMX: MX31: Cleanup include files and drop nasty #ifdef in driversStefano Babic2011-04-27-7/+2
| | | | | | | | | | As exception among the i.MX processors, the i.MX31 has headers without general names (mx31-regs.h, mx31.h instead of imx-regs.h and clock.h). This requires several nasty #ifdef in the drivers to include the correct header. The patch cleans up the driver and renames the header files as for the other i.MX processors. Signed-off-by: Stefano Babic <sbabic@denx.de>
* SPI: mxc_spi: replace fixed offsets with structuresStefano Babic2011-02-02-66/+28
| | | | | | | | This patch cleans driver code replacing all accesses to registers with fixed offsets with a corresponding structure. Signed-off-by: Stefano Babic <sbabic@denx.de>
* SPI: mxc_spi: add SPI clock calculation and setup to the driverAnatolij Gustschin2011-02-02-1/+22
| | | | | | | | | | | | | The MXC SPI driver didn't calculate the SPI clock up to now and just used highest possible divider 512 for DATA RATE in the control register. This results in very low transfer rates. The patch adds code to calculate and setup the SPI clock frequency for transfers. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefano Babic <sbabic@denx.de>
* SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx caseAnatolij Gustschin2011-02-02-5/+4
| | | | | | | | | | | | | | | We need to shift only one time in each cycle in the swapping loop for unaligned tx case. Currently two byte shift operations are performed in each loop cycle causing zero gaps in the transmited data, so not all data scheduled for transmition is actually transmited. The proper swapping in unaligned rx case is missing, so add it as we need to put the received data into the rx buffer in the correct byte order. Signed-off-by: Anatolij Gustschin <agust@denx.de> Tested-by: Stefano Babic <sbabic@denx.de>
* SPI: mxc_spi: add support for i.MX35 processorStefano Babic2011-02-02-24/+72
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51Stefano Babic2010-09-30-38/+111
| | | | | | | | | | | | | | | | | | | | The actual SPI driver for i.MX31 and i.MX51 controller use a wrong byte ordering, because it is supposed to work only with Freescale's devices, as the Power Controllers (PMIC). The driver is not suitable for general purposes, because the buffers passed to spi_xfer must be 32-bit aligned, as it is used mainly to send integer to PMIC devices. The patch drops any kind of limitation and makes the driver useful with devices controlled sending commands composed by single bytes (or by a odd number of bytes), such as spi flash, sensor, etc. Because the byte ordering is changed, any current driver using this controller must be adapted, too. Signed-off-by: Stefano Babic <sbabic@denx.de>
* MXC: Correct SPI_CPOL setting in SPI driverStefano Babic2010-09-30-2/+2
| | | | | | | | | | | | | | | | The handling of the SPI_CPOL bit inside the SPI driver was wrong. As reported by the manual, the meaning of the SSPOL inside the configuration register is the same as reported by SPI specification (0 if low in idle, 1 is high on idle). The driver inverts this logic. Because this patch sets the logic as specified, it is required to clear the CPOL bit in the configuration file to adapt to the correct logic. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: David Jander <david.jander@protonic.nl>
* Use common function to set GPIOs for MX3 and MX5Stefano Babic2010-09-29-8/+7
| | | | | | | | | The patch adds support for setting gpios to the MX51 processor and change name to the corresponding functions for MX31. In this way, it is possible to get rid of nasty #ifdef switches related to the processor type. Signed-off-by: Stefano Babic <sbabic@denx.de>
* SPI: added support for MX51 to mxc_spiStefano Babic2010-05-05-20/+211
| | | | | | This patch add SPI support for the MX51 processor. Signed-off-by: Stefano Babic <sbabic@denx.de>
* SPI: Fix 32 bit transfers in mxc_spi.cMagnus Lilja2010-02-12-0/+9
| | | | | | | | | | | | | | Commit f9b6a1575d9f1ca192e4cb60e547aa66f08baa3f, "i.MX31: fix SPI driver for shorter than 32 bit" broke 32 bit transfers. This patch makes single 32 bit transfer work again. Transfer lengths that are known not to work will abort and print an error message. Tested on i.MX31 Litekit and i.MX31 PDK using 32 bit transfers to the MC13783/ATLAS chip (using the 'date' command). Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* i.MX31: support GPIO as a chip-select in the mxc_spi driverGuennadi Liakhovetski2009-02-24-8/+56
| | | | | | | | | Some SPI devices have special requirements on chip-select handling. With this patch we can use a GPIO as a chip-select and strictly follow the SPI_XFER_BEGIN and SPI_XFER_END flags. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* i.MX31: fix SPI driver for shorter than 32 bitGuennadi Liakhovetski2009-02-24-11/+20
| | | | | | | | Fix setting the SPI Control register, 8 and 16-bit transfers and a wrong pointer in the free routine in the mxc_spi driver. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* SPI API improvementsHaavard Skinnemoen2008-06-03-31/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-1/+1
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* New i.MX31 SPI driverGuennadi Liakhovetski2008-04-18-0/+166
This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>