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path: root/drivers/pci
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* dm: pci: Add an inline API to test if a device is on a PCI busBin Meng2015-09-16-2/+2
| | | | | | | | Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pcie_imx: Use 'ms' for millisecondsFabio Estevam2015-09-13-3/+3
| | | | | | | milliseconds should be written as 'ms' instead of 'mS'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Marek Vasut <marex@denx.de>
* dm: pci: Allow a PCI bus to be found without an aliasSimon Glass2015-09-09-4/+24
| | | | | | | | | | | | | | At present, until a PCI bus is probed, it cannot be found by its sequence number unless it has an alias. This is the same with any device. However with PCI this is more annoying than usual, since bus 0 is always the same device. Add a function that tries a little harder to locate PCI bus 0. This means that PCI enumeration will happen automatically on the first access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci/layerscape: Setup mmu-masters property for the PCIeVarun Sethi2015-09-01-0/+9
| | | | | | | | | Setup mmu-masters property for the PCIe controllers. This would be used by the Linux SMMU driver, while setting up stream ID table mappings for the PCIe devices. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* dm: pci: Optimize pci_uclass_post_bind()Bin Meng2015-08-26-0/+7
| | | | | | | | If there is no pci device listed in the device tree, don't bother scanning the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()Bin Meng2015-08-26-2/+2
| | | | | | | | In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr. Mask bus number before save it to pplat->devfn. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe()Bin Meng2015-08-26-0/+21
| | | | | | | | | | | | | | | | | Per Intel FSP specification, we should call FSP notify API to inform FSP that PCI enumeration has been done so that FSP will do any necessary initialization as required by the chipset's BIOS Writer's Guide (BWG). Unfortunately we have to put this call here as with driver model, the enumeration is all done on a lazy basis as needed, so until something is touched on PCI it won't happen. Note we only call this after U-Boot is relocated and root bus has finished probing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Support selected device/driver binding before relocationBin Meng2015-08-26-11/+30
| | | | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. But we won't bind all devices found during the enumeration. Only devices whose driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic devices except bridges won't be bound. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Set up video framebuffer for coreboot before loading kernelBin Meng2015-08-26-2/+0
| | | | | | | | | Currenlty we only set up video framebuffer when VIDEO_VESA driver is used. With coreboot, VIDEO_COREBOOT driver is used instead. Since we already saved VESA mode in the VIDEO_COREBOOT driver, now we can also set up video framebuffer for coreboot before loading Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* video: coreboot: Save VESA mode for future useBin Meng2015-08-26-1/+1
| | | | | | | | When booting as a coreboot payload, the framebuffer details are passed from coreboot via configuration tables. We save these information into vesa_mode_info structure for future use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* pci: mvebu: Add PCIe driverAnton Schubert2015-08-17-0/+424
| | | | | | | | | | | | | | | | | | | This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the driver, this patch also removes the statically defined PCI MBUS windows. As they are not needed anymore, since this PCIe driver now creates the windows dynamically. Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000 PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp eval board using this Intel E1000 PCIe card in the PCIe 0 slot. This port was done in cooperation with Anton Schubert. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
* Revert "dm: pci: Allow scan bridge child devices before relocation"Simon Glass2015-08-14-0/+4
| | | | | | | | | | | | This reverts commit df189d9ba3f8fd1bc67e3c0c3c4ace16cd065ee1. Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices before relocation and there is not enough pre-reloc malloc() memory. Rathar then increase this memory, revert for now until we figure this out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a way to iterate through all PCI devicesSimon Glass2015-08-14-0/+60
| | | | | | | | | These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Provide friendly config access functionsSimon Glass2015-08-14-0/+76
| | | | | | | | | At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* lib/fdtdec: Fix compiling warning caused by changing fdt_addr_t typeYork Sun2015-08-06-5/+5
| | | | | | | | fdt_addr_t is changed to phys_addr_t. The format in debug should be updated to %pa to match the type. Signed-off-by: York Sun <yorksun@freescale.com> CC: Simon Glass <sjg@chromium.org>
* pci: Remove DEBUG from pci_compat.cBin Meng2015-08-05-1/+0
| | | | | | | Remove DEBUG in drivers/pci/pci_compat.c. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci: Indicate prefetchable memory allocate when debuggingSimon Glass2015-08-05-2/+3
| | | | | | | | | | At present the PCI output displays 'Mem' when it allocates memory for a PCI device, whether it is prefetchable or not. There is a distinction since the memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating prefetchable memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add a constant for an invalid interruptSimon Glass2015-08-05-1/+2
| | | | | | | Rather than using 0xff in the code, add a constant. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Fix up code for CONFIG_PCI_ENUM_ONLYSimon Glass2015-08-05-1/+3
| | | | | | | | This option is not used by any board but appears to still be useful, at least for testing. With recent commits it does not build, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Use debug() instead of DEBUGF() in pci_auto.cSimon Glass2015-08-05-25/+23
| | | | | | | | | This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Sanity test on vesa parameters before setting up kernel screen_infoBin Meng2015-08-05-0/+4
| | | | | | | | We should not set up kernel screen_info when the vesa parameters are insane, otherwise kernel will panic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Allow scan bridge child devices before relocationBin Meng2015-08-05-4/+0
| | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. Remove such limitation so that dm pci can be used before relocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers/pci/layerscape: Add EP mode supportMinghuan Lian2015-08-03-2/+135
| | | | | | | | | | | | | | | | The patch will initialize PCIe controller on EP mode 1. Setup bar: bar0 32bit 4K for specific configuration bar1 32bit 8K for MSIX bar2 64bit 4K for descriptor of memory bar4 64bit 1M for DMA memory test 2. Setup iATU: iATU inbound 0-3 to map bar transaction to memory address started at CONFIG_SYS_PCI_EP_MEMORY_BASE iATU outbound 0 to map 4G memory space Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* drivers/pci: Add function to find an extended capabilityMinghuan Lian2015-08-03-0/+53
| | | | | | | | | | PCIe extends device's configuration space to 4k and provides extended capability. The patch adds function to find them. The code is ported from Linux PCIe driver. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
* dm: pci: Support bridge device configuration correctlyBin Meng2015-07-28-18/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Pass only device/function to pci_bus_find_devfn()Bin Meng2015-07-28-1/+1
| | | | | | | | In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf which includes a bus number, but it really should not as this routine only expects a device/function encoding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Use complete bdf in all pci config read/write routinesBin Meng2015-07-28-27/+27
| | | | | | | | | | | | | | | | Currently pci_bus_read_config() and pci_bus_write_config() are called with bus number masked off in the parameter bdf, and bus number is supposed to be added back in the bridge driver's pci config read/write ops if the device is behind a pci bridge. However this logic only works for a pci topology where there is only one bridge off the root controller. If there is addtional bridge in the system, the logic will create a non-existent bdf where its bus number gets accumulated across bridges. To correct this, we change all pci config read/write routines to use complete bdf all the way up to the root controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct primary/secondary/subordinate bus number assignmentBin Meng2015-07-28-0/+9
| | | | | | | | | In driver model, each pci bridge device has its own hose structure. hose->first_busno points to the bridge device's device number, so we should not substract hose->first_busno before programming the bridge device's primary/secondary/subordinate bus number registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to get the BDF for a deviceSimon Glass2015-07-21-12/+11
| | | | | | | | | It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Add support for PCI driver matchingSimon Glass2015-07-21-13/+116
| | | | | | | | | | | | | | | | | | | At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder2015-07-20-0/+62
| | | | | | | | | | | This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci: Disable expansion ROM address decoding when signature check failsBin Meng2015-07-14-0/+4
| | | | | | | | | | We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter <mporter@konsulko.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* pci: Configure expansion ROM during auto config processBin Meng2015-07-14-31/+22
| | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-2/+6
| | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Tidy up the generic x86 PCI driverSimon Glass2015-07-14-5/+8
| | | | | | | | This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-14-0/+28
| | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
* x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-2/+2
| | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* video: Add 32-bit color depth support for VBEJian Luo2015-07-14-0/+1
| | | | | | | | | | The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-14-1/+1
| | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-14-1/+11
| | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-08-1/+3
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| * pci: imx: display message if no pcie linkTim Harvey2015-05-28-1/+3
| | | | | | | | | | | | | | If CONFIG_PCI_SCAN_SHOW enabled then lets print a message of no link was detected. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-06-05-0/+1
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| * | dm: pci: Allow PCI bus numbering aliasesSimon Glass2015-06-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed the default uclass behaviour to not support bus numbering. This is incorrect for PCI and that commit should have enabled the flag for PCI. Enable it so that PCI buses can be found and the 'pci' command works again. Also add a test for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | pci: Do not skip legacy IDE device configurationBin Meng2015-06-04-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The legacy IDE device has a BAR4 (Bus Master Interface BAR) which needs to be configured. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | pci: Allow debug message output in pci_auto.cBin Meng2015-06-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the '#undef DEBUG' in pci_auto.c so that we can enable debug message output via '-DDEBUG'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | pci: Move pci_hose_phys_to_bus() to pci_common.cBin Meng2015-06-04-70/+66
|/ / | | | | | | | | | | | | | | pci_hose_phys_to_bus() is needed by several drivers. Move it to pci_common.c to avoid a broken build when CONFIG_DM_PCI is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | pci: display header for bus scanTim Harvey2015-05-27-0/+4
|/ | | | | | | If we are displaying detected PCI devices (CONFIG_PCI_SCAN_SHOW) display a 'PCI:' header prior to scan. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2015-05-05-1/+22
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| * fsl/pci: Set CFG_READY for PCIe v3.0 and laterMinghuan Lian2015-05-04-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-10 03:13:05 +0000