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authorSimon Glass <sjg@chromium.org>2015-07-03 18:28:27 -0600
committerSimon Glass <sjg@chromium.org>2015-07-14 18:03:19 -0600
commitb9da5086b88a1565c7aede14e68bef2456c44475 (patch)
treef4817c1fc0bfa495fc69a15089da614e84af561f /drivers/pci
parentb71f9dca89013b8b100006029c98d04b495ebdf7 (diff)
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dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci-uclass.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index edec93f..5b91fe3 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -444,6 +444,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
{
int pci_addr_cells, addr_cells, size_cells;
int cells_per_record;
+ phys_addr_t addr;
const u32 *prop;
int len;
int i;
@@ -494,8 +495,11 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
}
/* Add a region for our local memory */
- pci_set_region(hose->regions + hose->region_count++, 0, 0,
- gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ addr = gd->ram_size;
+ if (gd->pci_ram_top && gd->pci_ram_top < addr)
+ addr = gd->pci_ram_top;
+ pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
return 0;
}