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* armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder2015-07-20-0/+62
| | | | | | | | | | | This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci: Disable expansion ROM address decoding when signature check failsBin Meng2015-07-14-0/+4
| | | | | | | | | | We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter <mporter@konsulko.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* pci: Configure expansion ROM during auto config processBin Meng2015-07-14-31/+22
| | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-2/+6
| | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Tidy up the generic x86 PCI driverSimon Glass2015-07-14-5/+8
| | | | | | | | This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-14-0/+28
| | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
* x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-2/+2
| | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* video: Add 32-bit color depth support for VBEJian Luo2015-07-14-0/+1
| | | | | | | | | | The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-14-1/+1
| | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-14-1/+11
| | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-08-1/+3
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| * pci: imx: display message if no pcie linkTim Harvey2015-05-28-1/+3
| | | | | | | | | | | | | | If CONFIG_PCI_SCAN_SHOW enabled then lets print a message of no link was detected. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-06-05-0/+1
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| * | dm: pci: Allow PCI bus numbering aliasesSimon Glass2015-06-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed the default uclass behaviour to not support bus numbering. This is incorrect for PCI and that commit should have enabled the flag for PCI. Enable it so that PCI buses can be found and the 'pci' command works again. Also add a test for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | pci: Do not skip legacy IDE device configurationBin Meng2015-06-04-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The legacy IDE device has a BAR4 (Bus Master Interface BAR) which needs to be configured. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | pci: Allow debug message output in pci_auto.cBin Meng2015-06-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the '#undef DEBUG' in pci_auto.c so that we can enable debug message output via '-DDEBUG'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | pci: Move pci_hose_phys_to_bus() to pci_common.cBin Meng2015-06-04-70/+66
|/ / | | | | | | | | | | | | | | pci_hose_phys_to_bus() is needed by several drivers. Move it to pci_common.c to avoid a broken build when CONFIG_DM_PCI is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | pci: display header for bus scanTim Harvey2015-05-27-0/+4
|/ | | | | | | If we are displaying detected PCI devices (CONFIG_PCI_SCAN_SHOW) display a 'PCI:' header prior to scan. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2015-05-05-1/+22
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| * fsl/pci: Set CFG_READY for PCIe v3.0 and laterMinghuan Lian2015-05-04-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PCIe controllers v3.0 and later need to set bit CFG_READY to allow all inbound configuration transactions to be processed normally when in EP mode. However, bit CFG_READY has been moved from PCIe configuration space to CCSR PCIe configuration register comparing previous version. The patch is to set this bit according to PCIe version. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issueZhao Qiang2015-05-04-0/+15
| | | | | | | | | | | | | | | | | | T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | pci: Remove parameter 'class' of pci_rom_load()Bin Meng2015-04-29-2/+2
| | | | | | | | | | | | | | pci_rom_load() does not use its parameter 'class', so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | pci: Option rom class is a 24-bit numberBin Meng2015-04-29-9/+11
|/ | | | | | | We should pass a u32 class number to pci_rom_probe() instead of a u16. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci/layerscape: fix link and class issues to support ls2085aMinghuan Lian2015-04-21-14/+33
| | | | | | | | | | | | | | 1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG to show the link status, so the patch fixes it. 2. Increase the delay time to make sure that link training has finished. 3. Return invalid value when accessing multi-function device 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we must set this bit before change DBI register value. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci/layerscape: remove unnecessary pcie_layerscape.hMinghuan Lian2015-04-21-3/+2
| | | | | | | | | | The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
* dm: x86: pci: Add a PCI driver for driver modelSimon Glass2015-04-18-0/+25
| | | | | | | Add a simple x86 PCI driver which uses standard functions provided by the architecture. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: sandbox: pci: Add a PCI emulation uclassSimon Glass2015-04-16-0/+68
| | | | | | | | Since sandbox does not have real devices (unless it borrows those from the host) it must use emulations. Provide a uclass which permits PCI operations to be passed through to an emulation device. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: sandbox: Add a simple PCI driverSimon Glass2015-04-16-0/+90
| | | | | | | Add a driver which can access emulations of devices and make them available in sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Add a uclass for PCISimon Glass2015-04-16-4/+714
| | | | | | | | | | | Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Move common PCI functions into their own fileSimon Glass2015-04-16-276/+299
| | | | | | | Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org>
* driver/pci: add Layerscape PCIe driverMinghuan Lian2015-02-24-5/+466
| | | | | | | | The patch adds Freescale Layerscape PCIe driver and provides up to 4 controllers support. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* PCI: add 64-bit prefetchable memory supportDavid Feng2015-02-16-1/+35
| | | | | | | | | | | PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: video: Allow video ROM execution to fall back to the other methodSimon Glass2015-02-05-7/+25
| | | | | | | | If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add a function to find a device by classSimon Glass2015-02-05-0/+43
| | | | | | | | There is an existing function prototype in the header file but it is not implemented. Implement something similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* drivers/pci/pci_rom.c: fix compile warning under 64bit modeMinghuan Lian2015-01-30-1/+1
| | | | | | | | | Fix this: drivers/pci/pci_rom.c:95:15: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] rom_header = (struct pci_rom_header *)rom_address; Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
* pci: tegra: Fix port information parsingSjoerd Simons2015-01-23-3/+2
| | | | | | | | | | | | | commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the new fdtdec pci helpers. To get the device index of the root port, the "reg" property should be parsed from the dtb (as was previously the case). With this patch i can successfully network boot my jetson tk1 Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
* x86: Access the VGA ROM when neededSimon Glass2015-01-23-2/+33
| | | | | | | Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Don't stop when we get a vendor/device mismatchSimon Glass2015-01-23-1/+1
| | | | | | | These are quite common and we may as well press on and not be so picky. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support ROMs on other archsSimon Glass2015-01-23-0/+6
| | | | | | | | We shouldn't assume that the VGA ROM can always be loaded at c0000. This is only true on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Correct endianness isues in pci_romSimon Glass2015-01-23-11/+14
| | | | | | | | This code is too x86-dependent at present. Correct it so that it can run on big-endian machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* powerpc: 74xx_7xx: remove 74xx_7xx cpu supportMasahiro Yamada2015-01-16-5/+0
| | | | | | | | | | | | | All the 74xx_7xx boards are still non-generic boards: P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2 Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Nye Liu <nyet@zumanetworks.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
* x86: pci: Display vesa modes in hexSimon Glass2015-01-13-2/+2
| | | | | | | | The hex value is more commonly understood, so use that instead of decimal. Add a 0x prefix to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: video: Add debug option to time the BIOS copySimon Glass2015-01-13-0/+3
| | | | | | | | This can be very slow - typically 80ms even on a fast machine since it uses the SPI flash to read the data. Add an option to display the time taken. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Don't return a vesa mode when there is not videoSimon Glass2015-01-13-1/+1
| | | | | | | If the video has not been set up, we should not return a success code. This can be detected by seeing if any of the variables are non-zero. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Add several apis to decode pci device nodeBin Meng2015-01-13-1/+2
| | | | | | | | | | | | | | This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including: - fdtdec_get_pci_addr() for encoded pci address - fdtdec_get_pci_vendev() for vendor id and device id - fdtdec_get_pci_bdf() for pci device bdf triplet - fdtdec_get_pci_bar32() for pci device register bar Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
* pci: Make pci apis usable before relocationBin Meng2015-01-12-8/+17
| | | | | | | | | | | | | | Introduce a gd->hose to save the pci hose in the early phase so that apis in drivers/pci/pci.c can be used before relocation. Architecture codes need assign a valid gd->hose in the early phase. Some variables are declared as static so change them to be either stack variable or global data member so that they can be used before relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which just affects some print format. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci: tegra: Add Tegra PCIe driverThierry Reding2014-12-18-0/+1144
| | | | | | | | | | | | | | | Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+52
| | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pci: Add general support for execution of video ROMsSimon Glass2014-11-25-1/+279
| | | | | | | | | | | | | | | | | | Some platforms don't have native code for dealing with their video hardware. In some cases they use a binary blob to set it up and perform required actions like setting the video mode. This approach is a hangover from the old PC days where a ROM was provided and executed during startup. Even now, these ROMs are supplied as a way to set up video. It avoids the code for every video chip needing to be provided in the boot loader. But it makes the video much less flexible - e.g. it is not possible to do anything else while the video init is happening (including waiting hundreds of milliseconds for display panels to start up). In any case, to deal with this sad state of affairs, provide an API for execution of x86 video ROMs, either natively or through emulation. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Add functions to read and write a BAR addressSimon Glass2014-11-25-3/+21
| | | | | | | | | Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-10 16:27:36 +0000