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* dm: pci: Convert bios_emu to use the driver model PCI APISimon Glass2016-01-24-3/+3
| | | | | | | | At present this BIOS emulator uses a bus/device/function number. Change it to use a device if CONFIG_DM_PCI is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Avoid using pci_bus_to_hose() in the uclassSimon Glass2016-01-24-7/+7
| | | | | | | | | This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to write a BARSimon Glass2016-01-24-0/+8
| | | | | | | | Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move pci_bus_to_hose() to compatibilitySimon Glass2016-01-24-15/+28
| | | | | | | | This function should not be used by driver-model code, so move it to the compatibility portion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci_rom.c: Fix may be used uninitialized warningTom Rini2016-01-19-1/+1
| | | | | | | | | | | | | | With gcc-5.x we get: drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios': drivers/pci/pci_rom.c:352:3: warning: 'ram' may be used uninitialized in this function [-Wmaybe-uninitialized] While unconvinced that this can happen in practice (if we malloc we set alloced to true, it will be false otherwise), silence the compiler. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: pci: Avoid a memory leak when allocating the ROMSimon Glass2016-01-15-12/+33
| | | | | | | | | | Adjust pci_rom_load() to return an indication of whether it allocated memory or not. Adjust the caller to free it. This fixes a memory leak when PCI_VGA_RAM_IMAGE_START is not used. Reported-by: Coverity (CID: 134194) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* dm: pci: Add a 'fall through' commentSimon Glass2016-01-15-0/+1
| | | | | | | | | For this class it is intended to set up the PCI device, so add a comment to indicate this. This avoids a coverity warning. Reported-by: Coverity (CID: 134194) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers/pci/pci_mvebu: Fix for boards with X4 lanesPhil Sutter2016-01-14-0/+14
| | | | | | | | | | | | | | | | | Armada XP has support for X4 lanes, boards specify this in their serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration is stored in GEN_PURP_RES_2_REG. When enumerating PEX, subsequent interfaces of an X4 lane must be skipped. Otherwise the enumeration hangs up the board. The way this is implemented here is not exactly beautiful, but it mimics how Marvell's BSP does it. Alternatively we could get the information using board_serdes_cfg_get(), but that won't lead to clean code, either. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers/pci: Fix for debug builds without CONFIG_PCI_ENUM_ONLYPhil Sutter2016-01-14-1/+1
| | | | | | | | | | The debug printing references bar_res, which exists only if CONFIG_PCI_ENUM_ONLY is not defined. Therefore move it into the ifdef'd area. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* pci: Tidy up comments in pci_bind_bus_devices()Simon Glass2016-01-12-3/+1
| | | | | | | | | The current comments are confusing. We don't actually bind a generic device when the device tree has no information. We try to scan available PCI drivers. Update the comments to reflect this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Switch to DM API for PCI address mappingSimon Glass2016-01-12-1/+1
| | | | | | | | We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add driver model API functions for address mappingSimon Glass2016-01-12-0/+136
| | | | | | | | At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Drop the old version of pci_find_class()Simon Glass2016-01-12-42/+42
| | | | | | | | Move this function into the compatibility file so that it is not available by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Drop the old version of pci_find_device/s()Simon Glass2016-01-12-0/+2
| | | | | | | | Move these functions into the compatibility file so that they are not available by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: pci: Adjust bios_run_on_x86() to use the DM PCI APISimon Glass2016-01-12-2/+2
| | | | | | | | This function should take a struct udevice rather than pci_dev_t. Update it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: video: Convert video and pci_rom to use DM PCI APISimon Glass2016-01-12-28/+26
| | | | | | | | | | Adjust these files to use the driver-model PCI API instead of the legacy functions. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to read a PCI BARSimon Glass2016-01-12-0/+13
| | | | | | | Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a driver-model version of pci_find_class()Simon Glass2016-01-12-0/+20
| | | | | | | | | Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a driver-model version of pci_find_device()Simon Glass2016-01-12-0/+39
| | | | | | | | | Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Use driver model PCI API in auto-configSimon Glass2016-01-12-62/+444
| | | | | | | | | | | | | At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a dm_ prefix to pci_bus_find_bdf()Simon Glass2016-01-12-1/+1
| | | | | | | | | | | | Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a dm_ prefix to pci_get_bdf()Simon Glass2016-01-12-5/+6
| | | | | | | | | | | | Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Mark legacy files as suchSimon Glass2016-01-12-4/+10
| | | | | | | | We don't want people changing the legacy PCI files while migration is in progress. Update the file headers to indicate that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: layerscape: Adjust the return value when ls_pcie_addr_valid() failsBin Meng2016-01-08-1/+1
| | | | | | | | | When trying to access non-existent/unsupported PCI devices in ls_pcie_read_config(), when ls_pcie_addr_valid() fails it returns error code and fills in the result with 0xffffffff manually. But it really should return zero to upper layer codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* pci: imx: Adjust the return value when imx_pcie_addr_valid() failsBin Meng2016-01-08-1/+1
| | | | | | | | | | | When trying to access non-existent/unsupported PCI devices in imx_pcie_read_config(), when imx_pcie_addr_valid() fails it returns error code and fills in the result with 0xffffffff manually. But it really should return zero to upper layer codes. Reported-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
* x86: Remove HAVE_ACPI_RESUMEBin Meng2015-12-09-8/+0
| | | | | | | | | These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* dm: pci: Disable PCI compatibility functions by defaultSimon Glass2015-12-01-1/+11
| | | | | | | | | We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move common auto-config functions to a common fileSimon Glass2015-12-01-117/+129
| | | | | | | | Some functions will be used by driver model and legacy PCI code. To avoid duplication, put these in a separate, shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Rename pci_auto.c to pci_auto_old.cSimon Glass2015-12-01-1/+1
| | | | | | | | This file should not be used with driver model as it has lots of legacy/ compatibility functions. Rename it to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: tegra: pci: Convert tegra boards to driver model for PCISimon Glass2015-12-01-322/+155
| | | | | | | | | Adjust the Tegra PCI driver to support driver model and move all boards over at the same time. This can make use of some generic driver model code, such as the range-decoding logic. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add a function to find the regions for a PCI busSimon Glass2015-12-01-0/+30
| | | | | | | | | This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add a function to get the controller for a busSimon Glass2015-12-01-0/+8
| | | | | | | | | A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add functions to emulate 8- and 16-bit accessSimon Glass2015-12-01-0/+39
| | | | | | | | | Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Support decoding ranges with duplicate entriesSimon Glass2015-12-01-3/+10
| | | | | | | | | | | | | | | | | | At present we add a new resource entry for every range entry. But some range entries refer to configuration regions. To make this work, avoid adding two regions of the same type. The later ranges will overwrite the earlier (configuration) ones. There does not seem to be a way to distinguish the configuration ranges other than by ordering (as per the device tree binding). We could perhaps instead just store one region of each type in a simple array. Once we are sure that we don't need to support multiple regions, we could change this. It would be easier to do it when all drivers are converted to use driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Set up the SDRAM mapping correctlySimon Glass2015-12-01-6/+9
| | | | | | | | | | SDRAM doesn't always start at 0. Adjust the region mapping so that it works on platforms where SDRAM is somewhere else. This needs testing on other platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: tegra: pci: Move CONFIG_PCI_TEGRA to KconfigSimon Glass2015-12-01-0/+10
| | | | | | | Move this option to Kconfig and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* pci/layerscape: add support for LS1043A PCIe LUT register accessMingkai Hu2015-11-30-7/+7
| | | | | | | | | | | The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-1/+1
| | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-1/+1
| | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
* pci: fix address range check in __pci_hose_phys_to_bus()Marcel Ziswiler2015-11-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The address range check may overflow if the memory region is located at the top of the 32-bit address space. This can e.g. be seen on TK1 if using the E1000 gigabit Ethernet driver where start and size are both 0x80000000 leading to the following messages: Apalis TK1 # tftpboot $loadaddr test_file Using e1000#0 device TFTP from server 192.168.10.1; our IP address is 192.168.10.2 Filename 'test_file'. Load address: 0x80408000 Loading: pci_hose_phys_to_bus: invalid physical address This patch fixes this by changing the order of the addition vs. subtraction in the range check just like already done in __pci_hose_bus_to_phys(). Reported-by: Ivan Mercier <ivan.mercier@nexvision.fr> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-11-12-6/+77
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| * pci: tegra: add/enable support for Tegra210Stephen Warren2015-11-12-0/+22
| | | | | | | | | | | | | | | | | | This needs a separate compatible value from Tegra124 since the new HW version has bugs that would prevent a driver for previous HW versions from operating at all. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: call tegra_pcie_board_init() earlierStephen Warren2015-11-12-2/+2
| | | | | | | | | | | | | | | | | | | | The board PCI setup code may control regulators that are required simply to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move the call to this function earlier so that all board-provided resources are ready early enough for everything to work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: implement PCA enable workaroundStephen Warren2015-11-12-0/+14
| | | | | | | | | | | | | | | | | | | | Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: use #address-/size-cells from DTStephen Warren2015-11-12-3/+30
| | | | | | | | | | | | | | | | | | The number of cells used by each entry in the DT ranges property is determined by the #address-cells/#size-cells properties. Fix the code to respect this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: clip RAM size to 32-bitsStephen Warren2015-11-12-1/+9
| | | | | | | | | | | | | | | | | | Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | pci: fix checking PCI_REGION_MEM in pci_hose_phys_to_bus()Cheng Gu2015-11-12-2/+2
|/ | | | | | | | | | | | | | | When converting between PCI bus and phys addresses, a two pass search was introduced with preference to non-PCI_REGION_SYS_MEMORY regions. See commit 2d43e873a29ca4959ba6a30fc7fb396d3fd0dccf. However, since PCI_REGION_MEM is defined as 0, the if statement was always asserted true: ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) This patch uses PCI_REGION_TYPE bit to check if the region is PCI_REGION_MEM: ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) Signed-off-by: Cheng Gu <chenggu@marvell.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-1/+3
| | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* dm: pci: Enable VGA address forwarding on bridgesBin Meng2015-10-21-0/+18
| | | | | | | | | To support graphics card behind a PCI bridge, the bridge control register (offset 0x3e) in the configuration space must turn on VGA address forwarding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Fix pci_last_busno() to return the real last bus noBin Meng2015-10-21-24/+1
| | | | | | | | | Currently pci_last_busno() only checks the last bridge device under the first UCLASS_PCI device. This is not the case when there are multiple bridge devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-24 00:36:40 +0000