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authorSimon Glass <sjg@chromium.org>2015-11-19 20:26:57 -0700
committerSimon Glass <sjg@chromium.org>2015-12-01 06:26:36 -0700
commit2084c5af6dc03b500622ae8844bc69cc5a8e51fb (patch)
treebe9de994822a5b57318bf3cf3554dda701c57090 /drivers/pci
parent871bc923740538959dff818f382cbcce0282fa52 (diff)
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dm: pci: Set up the SDRAM mapping correctly
SDRAM doesn't always start at 0. Adjust the region mapping so that it works on platforms where SDRAM is somewhere else. This needs testing on other platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci-uclass.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 1d93194..6d860c4 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -680,8 +680,8 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
int parent_node, int node)
{
int pci_addr_cells, addr_cells, size_cells;
+ phys_addr_t base = 0, size;
int cells_per_record;
- phys_addr_t addr;
const u32 *prop;
int len;
int i;
@@ -732,11 +732,14 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
}
/* Add a region for our local memory */
- addr = gd->ram_size;
- if (gd->pci_ram_top && gd->pci_ram_top < addr)
- addr = gd->pci_ram_top;
- pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+ size = gd->ram_size;
+#ifdef CONFIG_SYS_SDRAM_BASE
+ base = CONFIG_SYS_SDRAM_BASE;
+#endif
+ if (gd->pci_ram_top && gd->pci_ram_top < base + size)
+ size = gd->pci_ram_top - base;
+ pci_set_region(hose->regions + hose->region_count++, base, base,
+ size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
return 0;
}