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* | dm: sf: Add support for all targets which requires MANUAL_RELOCMichal Simek2015-11-19-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is follow up patch based on "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) to update function pointers for DM. Using post_bind is not ideal but it is one on current option what can be used. Variable reloc_done has to be used do not call relocation after every bind. Maybe new core functions should be introduced for this case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | spl: change return values of spl_*_load_image()Nikita Kiryanov2015-11-18-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make spl_*_load_image() functions return a value instead of hanging if a problem is encountered. This enables main spl code to make the decision whether to hang or not, thus preparing it to support alternative boot devices. Some boot devices (namely nand and spi) do not hang on error. Instead, they return normally and SPL proceeds to boot the contents of the load address. This is considered a bug and is rectified by hanging on error for these devices as well. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | altera_qspi: change ioremap to map_physmemThomas Chou2015-11-18-1/+1
|/ | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* sf: Fix NULL pointer exception for flashes without lock methodsBin Meng2015-11-13-6/+12
| | | | | | | | | | | commit c3c016c "sf: Add SPI NOR protection mechanism" introduced flash_lock()/flash_unlock()/flash_is_locked() methods for SPI flash, but not every flash driver supplies these. We should test these methods against NULL before actually calling them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* mtd: uboot: Add meaningful error messageMaxime Ripard2015-11-12-1/+1
| | | | | | | | | | The current error message in get_part if CONFIG_MTDPARTS is disabled is "offset is not a number" which is confusing and doesn't help at all. Change that for something that might give a hint on what's going on. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mtd: add altera quadspi driverThomas Chou2015-11-12-0/+283
| | | | | | | | Add Altera Generic Quad SPI Controller support. The controller converts SPI NOR flash to parallel flash interface. So it is not like other SPI flash, but rather like CFI flash. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* cfi_flash: convert to driver modelThomas Chou2015-11-12-0/+89
| | | | | | | Convert cfi flash to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: implement a MTD uclassThomas Chou2015-11-12-0/+34
| | | | | | | | | | | | Implement a Memory Technology Device (MTD) uclass. It should include most flash drivers in the future. Though no uclass ops are defined yet, the MTD ops could be used. The NAND flash driver is based on MTD. The CFI flash and SPI flash support MTD, too. It should make sense to convert them to MTD uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* sf: Add SPI NOR protection mechanismFabio Estevam2015-11-05-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | Many SPI flashes have protection bits (BP2, BP1 and BP0) in the status register that can protect selected regions of the SPI NOR. Take these bits into account when performing erase operations, making sure that the protected areas are skipped. Tested on a mx6qsabresd: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB => sf protect lock 0x3f0000 0x10000 => sf erase 0x3f0000 0x10000 offset 0x3f0000 is protected and cannot be erased SF: 65536 bytes @ 0x3f0000 Erased: ERROR => sf protect unlock 0x3f0000 0x10000 => sf erase 0x3f0000 0x10000 SF: 65536 bytes @ 0x3f0000 Erased: OK Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> [re-worked to fit the lock common to dm and non-dm] Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* sf: Add SPI protection mechanism from the kernelFabio Estevam2015-11-05-0/+173
| | | | | | | | | | | | | | | | | | Add the SPI NOR protection mechanism from the kernel. This code is based on the work from Brian Norris <computersforpeace@gmail.com> Here is the commit details: "mtd: spi-nor: refactor block protection functions" (sha1: 62593cf40b23b523b9fc9334ca61ba6c595ebb09) Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* compat: Remove is_power_of_2() definitionFabio Estevam2015-11-05-2/+2
| | | | | | | | | | Use the is_power_of_2() definition from log2.h to align with the kernel implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-10-28-100/+115
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| * sf: Add FSR support to spi_flash_cmd_wait_readyJagan Teki2015-10-25-9/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds flag status register reading support to spi_flash_cmd_wait_ready. Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Hou Zhiqiang <B48286@freescale.com> Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Update status reg check in spi_flash_cmd_wait_readyJagan Teki2015-10-25-58/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current flash wait_ready logic is not modular to add new register status check, hence updated the status check for adding few more register checks in future. Below are the sf speed runs with 'sf update' on whole flash, 16MiB. => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.564s, speed 289262 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 62.549s, speed 275036 B/s => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 61.276s, speed 284359 B/s Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Tom Rini <trini@konsulko.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * sf: Make flash->flags use for generic usageJagan Teki2015-10-25-5/+9
| | | | | | | | | | | | | | | | | | | | Use the flash->flags for generic usage, not only for dm-spi-flash, this will be used for future flag additions. [Correct the spi flash flags detect logic] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Optimize BAR write codeJagan Teki2015-10-25-28/+13
| | | | | | | | | | | | | | | | | | | | Optimized spi-flash bar writing code and also removed unnecessary bank_sel in read_ops. Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Add spi_flash_read_barJagan Teki2015-10-25-19/+34
| | | | | | | | | | | | | | | | | | Add spi_flash_read_bar function for reading bar and discovering bar commands at probe time. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Return bank_sel, if flash->bank_curr == bank_selJagan Teki2015-10-25-1/+1
| | | | | | | | | | | | | | | | | | If computed bank_sel is same as flash->bank_curr which is computed at probe time, then return the bank_sel instead of zero. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: params: Add IS25LP128 part supportJagan Teki2015-10-25-0/+1
| | | | | | | | | | | | | | | | Added support for IS25LP128 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
| * sf: params: Add IS25LP064 part supportJagan Teki2015-10-25-0/+1
| | | | | | | | | | | | | | | | Added support for IS25LP064 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
| * sf: params: Add IS25LP032 part supportJagan Teki2015-10-25-0/+3
| | | | | | | | | | | | | | | | Added support for IS25LP032 flash part. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com>
* | Merge git://www.denx.de/git/u-boot-cfi-flashTom Rini2015-10-27-41/+41
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| * | cfi_flash: use specific width types for cwordRyan Harkin2015-10-27-41/+41
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the cword union to use specific length types that are architecture indepented. This patch also renames the members of the cword union to represent their usage, i.e.: c -> w8 s -> w16 l -> w32 ll -> w64 Where "w" stands for "width" in bits. I discovered this problem when enabling CFI flash on vexpress64. cword.l was an unsigned long int, but it was intended to be 32 bits wide. Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a 64-bit system fails when attempting to use 32-bit wide CFI flash parts. Similar problems also existed with the other cword sizes. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-10-27-2/+2
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| * | dm: Rename dev_get_parentdata() to dev_get_parent_priv()Simon Glass2015-10-23-2/+2
| |/ | | | | | | | | | | | | | | The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | UBI: Fastmap: Fix PEB array typeHeiko Schocher2015-10-26-2/+2
| | | | | | | | | | | | | | | | | | The PEB array is an array of __be32, so let's fix the scan_pool() prototype accordingly. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Heiko Schocher <hs@denx.de>
* | ubi,ubifs: sync with linux v4.2Heiko Schocher2015-10-26-1347/+1860
|/ | | | | | | | | | | | | | | | | sync with linux v4.2 commit 64291f7db5bd8150a74ad2036f1037e6a0428df2 Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Aug 30 11:34:09 2015 -0700 Linux 4.2 This update is needed, as it turned out, that fastmap was in experimental/broken state in kernel v3.15, which was the last base for U-Boot. Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-10-15-109/+138
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| * mtd: nand: vf610_nfc: resync with upstream Linux versionStefan Agner2015-10-15-109/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This resyncs the driver changes with the Linux version of the driver. The driver received some feedback in the LKML and got recently acceppted, the latest version can be found here: https://lkml.org/lkml/2015/9/2/678 Notable changes are: - On ECC error, reread OOB and count bit flips in OOB too. If flipped bits are below threshold, also return an empty OOB buffer. - Return the amount of bit flips in vf610_nfc_read_page. - Use endianness aware vf610_nfc_read to read ECC status. - Do not enable IDLE IRQ (since we do not operate with an interrupt service routine). - Use type safe struct for buffer variants (vf610_nfc_alt_buf). - Renamed variables in struct vf610_nfc (column and page_sz) to reflect better what they really representing. The U-Boot version currently does not support RAW NAND write when using the HW ECC engine. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Scott Wood <scottwood@freescale.com>
* | nand: omap_gpmc: Change correctable bit-flips messages to debug()Ezequiel García2015-10-11-3/+3
| | | | | | | | | | | | | | | | Messages on corrected bit-flips are not really useful, as bit-flips are perfectly normal. Let's avoid cluttering the console and make them debug. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* | mtd: sf: Add support AT26DF081A chipYao Yuan2015-10-11-0/+1
| | | | | | | | | | | | | | | | AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card. We can access the flash through DSPI2 on LS1021ATWR board. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | sunxi_nand_spl: Be smarter about where to look for backup u-boot.binHans de Goede2015-09-29-6/+20
|/ | | | | | | | | | | | | | | | | | We know when u-boot is written to its own partition, in this case the layout always is: eb 0 spl eb 1 spl-backup eb 2 u-boot eb 3 u-boot-backup eb: erase-block So if we cannot load u-boot from its primary offset we know exactly where to look for it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mtd: nand: mxs check maximum ecc that platfrom supportsPeng Fan2015-09-20-1/+8
| | | | | | | | | | | | Check maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Han Xu <b45815@freescale.com> Tested-By: Tim Harvey <tharvey at gateworks.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()Stefan Roese2015-09-15-6/+15
| | | | | | | | | | | | | | | | | | | This patch addresses some comments raised by Scott in the last versions. Here the changes in detail: - Removed __maybe_unused as its not needed - Added check for strength == 4 and error out for the unsupported ECC strength values - Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this will be done in nand_scan_tail() - Set .caclulate back to fsmc_read_hwecc() in the HW case - Added comment that this function will only be called on SPEAr platforms, not supporting the BCH8 HW ECC (FSMC_VER8) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Scott Wood <scottwood@freescale.com>
* bitops: introduce BIT() definitionHeiko Schocher2015-09-11-1/+0
| | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-11-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* Move malloc_cache_aligned() to its own headerSimon Glass2015-09-11-0/+1
| | | | | | | | | | | | | | | | | | | At present malloc.h is included everywhere since it recently was added to common.h in this commit: 4519668 mtd/nand/ubi: assortment of alignment fixes This seems wasteful and unnecessary. We have been trying to trim down common.h and put separate functions into separate header files and that change goes in the opposite direction. Move malloc_cache_aligned() to a new header so that this can be avoided. The header would perhaps be better named as alignmem.h but it needs to be included after common.h and people might be confused by this. With the name memalign.h it fits nicely after malloc() in most cases. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600Stefan Roese2015-09-11-0/+40
| | | | | | | | | | | | | | | | | | | This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your config header: #define CONFIG_NAND_ECC_BCH #define CONFIG_BCH And use the command "nandecc bch4" to select this ECC scheme upon runtime. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
* arm: Remove nhk8815 boards and nomadik archSimon Glass2015-09-11-207/+0
| | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devicesStefan Roese2015-09-10-0/+1
| | | | | | | | | | This patch adds support for NAND chips with 4KiB page size and 24/1024 ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the ICnova-A20 SoM. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through KconfigHans de Goede2015-08-31-0/+9
| | | | | | | | | | | | | | Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends, to avoid double defining it for SoCs which have not yet moved to Kconfig for this. Having this in Kconfig is useful because this is something which may differ from one board to the other even when using the same SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Scott Wood <scottwood@freescale.com>
* sunxi_nand_spl: clear status flags in SPL implementationBoris Brezillon2015-08-31-3/+8
| | | | | | | | | | | Some status flags remain set until you explicetly clear the bit in the status register. Fix the SPL implementation to avoid false positive. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [hdegoede@redhat.com: Port from v2015.07 to v2015.10] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_ENDHans de Goede2015-08-31-10/+6
| | | | | | | | | | | | | | | | | We only ever use syndrome mode for the partitions which contain the SPL, as that is required for the BROM to be able to read the SPL. Instead of using some arbritray limit for deciding whether or not to use syndrome, be smart and check if u-boot-dtb.bin is directly behind the SPL, if it is not then it is on its own partition and we should not use syndrome. Note the reason why we only use syndrome mode for the SPL is because it comeswith weaker randomization, introducing a risk for more bit errors, so we want to avoid it when possible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXIHans de Goede2015-08-31-10/+10
| | | | | | | | | | | | | | | We eventually want to add full nand support, since it makes no sense to build SPL with nand support and u-boot without, or the other way around, a single option will suffice. Renaming the Kconfig option now makes things easier when we add full nand support in the future. The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an "ifdef CONFIG_SPL_BUILD" block in the Makefile. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Add support for backup boot partitionsHans de Goede2015-08-31-0/+16
| | | | | | | | | | | | | The BROM does not care / use bad page markings, instead it deals with any bad pages in the first erase-block by simply trying to load "boot0" from the next erase-block. This commit implements the same strategy for the sunxi spl nand code, allowing it to boot from the backup boot partition when the main boot partition is bad (tested by erasing the main boot partition). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Auto detect nand configuration parametersHans de Goede2015-08-31-29/+39
| | | | | | | | | | | | | | | | | | | Auto detect the nand configuration parameters, like the BROM does. This allows us to get rid of various Kconfig settings, and is necessary to support generic boards like the mk802 which have seen many production runs with different nands. The full blown u-boot/kernel nand driver uses the nand id to determine this info, for the SPL we do as the BROM does and simply try a few standard configs. Note the table only contains configs which are known to actually be used, rather then all the configs the BROM tries. This means that it may need to be updated in the future as we add support for nand on more boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Parametrize lowlevel read functionsHans de Goede2015-08-31-38/+48
| | | | | | | | | | | | Parametrize the lowlevel nand_read_page function, instead of directly using the CONFIG_foo settings for page-size, etc. there and add a few wrappers / helper functions for calling it. This is a preparation patch for adding auto-detecting of the nand parameters like the BROM does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Properly config page-size in the nand ctl registerHans de Goede2015-08-31-0/+5
| | | | | | | | | Properly config page-size in the nand ctl register, it seems that things work fine without doing this, but still lets play it safe and properly set the page-size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Add support for sun4i and sun5i SoCsHans de Goede2015-08-31-2/+2
| | | | | | | | | | | | Other then having a few less chip-select lines the nand controller on sun4i, sun5i and sun7i is identical. Note this patch also muxes GPC7 to the NAND on sun7i where as before it was not muxed this way. GPC7 is a standard NAND pin, so it should always be muxed to the NAND when in use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _offHans de Goede2015-08-31-46/+12
| | | | | | | | | Sync the code for figuring out the ecc_mode and ecc_offset with the linux kernel v4.1. Keeping this in sync seems like a good idea in general, and it fixes / adds support for ecc strengths of 56, 60 and 64 bits. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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