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* bitops: introduce BIT() definitionHeiko Schocher2015-09-11-1/+0
| | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-11-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* Move malloc_cache_aligned() to its own headerSimon Glass2015-09-11-0/+1
| | | | | | | | | | | | | | | | | | | At present malloc.h is included everywhere since it recently was added to common.h in this commit: 4519668 mtd/nand/ubi: assortment of alignment fixes This seems wasteful and unnecessary. We have been trying to trim down common.h and put separate functions into separate header files and that change goes in the opposite direction. Move malloc_cache_aligned() to a new header so that this can be avoided. The header would perhaps be better named as alignmem.h but it needs to be included after common.h and people might be confused by this. With the name memalign.h it fits nicely after malloc() in most cases. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600Stefan Roese2015-09-11-0/+40
| | | | | | | | | | | | | | | | | | | This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your config header: #define CONFIG_NAND_ECC_BCH #define CONFIG_BCH And use the command "nandecc bch4" to select this ECC scheme upon runtime. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
* arm: Remove nhk8815 boards and nomadik archSimon Glass2015-09-11-207/+0
| | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devicesStefan Roese2015-09-10-0/+1
| | | | | | | | | | This patch adds support for NAND chips with 4KiB page size and 24/1024 ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the ICnova-A20 SoM. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through KconfigHans de Goede2015-08-31-0/+9
| | | | | | | | | | | | | | Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends, to avoid double defining it for SoCs which have not yet moved to Kconfig for this. Having this in Kconfig is useful because this is something which may differ from one board to the other even when using the same SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Scott Wood <scottwood@freescale.com>
* sunxi_nand_spl: clear status flags in SPL implementationBoris Brezillon2015-08-31-3/+8
| | | | | | | | | | | Some status flags remain set until you explicetly clear the bit in the status register. Fix the SPL implementation to avoid false positive. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [hdegoede@redhat.com: Port from v2015.07 to v2015.10] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_ENDHans de Goede2015-08-31-10/+6
| | | | | | | | | | | | | | | | | We only ever use syndrome mode for the partitions which contain the SPL, as that is required for the BROM to be able to read the SPL. Instead of using some arbritray limit for deciding whether or not to use syndrome, be smart and check if u-boot-dtb.bin is directly behind the SPL, if it is not then it is on its own partition and we should not use syndrome. Note the reason why we only use syndrome mode for the SPL is because it comeswith weaker randomization, introducing a risk for more bit errors, so we want to avoid it when possible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXIHans de Goede2015-08-31-10/+10
| | | | | | | | | | | | | | | We eventually want to add full nand support, since it makes no sense to build SPL with nand support and u-boot without, or the other way around, a single option will suffice. Renaming the Kconfig option now makes things easier when we add full nand support in the future. The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an "ifdef CONFIG_SPL_BUILD" block in the Makefile. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Add support for backup boot partitionsHans de Goede2015-08-31-0/+16
| | | | | | | | | | | | | The BROM does not care / use bad page markings, instead it deals with any bad pages in the first erase-block by simply trying to load "boot0" from the next erase-block. This commit implements the same strategy for the sunxi spl nand code, allowing it to boot from the backup boot partition when the main boot partition is bad (tested by erasing the main boot partition). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Auto detect nand configuration parametersHans de Goede2015-08-31-29/+39
| | | | | | | | | | | | | | | | | | | Auto detect the nand configuration parameters, like the BROM does. This allows us to get rid of various Kconfig settings, and is necessary to support generic boards like the mk802 which have seen many production runs with different nands. The full blown u-boot/kernel nand driver uses the nand id to determine this info, for the SPL we do as the BROM does and simply try a few standard configs. Note the table only contains configs which are known to actually be used, rather then all the configs the BROM tries. This means that it may need to be updated in the future as we add support for nand on more boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Parametrize lowlevel read functionsHans de Goede2015-08-31-38/+48
| | | | | | | | | | | | Parametrize the lowlevel nand_read_page function, instead of directly using the CONFIG_foo settings for page-size, etc. there and add a few wrappers / helper functions for calling it. This is a preparation patch for adding auto-detecting of the nand parameters like the BROM does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Properly config page-size in the nand ctl registerHans de Goede2015-08-31-0/+5
| | | | | | | | | Properly config page-size in the nand ctl register, it seems that things work fine without doing this, but still lets play it safe and properly set the page-size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Add support for sun4i and sun5i SoCsHans de Goede2015-08-31-2/+2
| | | | | | | | | | | | Other then having a few less chip-select lines the nand controller on sun4i, sun5i and sun7i is identical. Note this patch also muxes GPC7 to the NAND on sun7i where as before it was not muxed this way. GPC7 is a standard NAND pin, so it should always be muxed to the NAND when in use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _offHans de Goede2015-08-31-46/+12
| | | | | | | | | Sync the code for figuring out the ecc_mode and ecc_offset with the linux kernel v4.1. Keeping this in sync seems like a good idea in general, and it fixes / adds support for ecc strengths of 56, 60 and 64 bits. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Add proper cache flusingHans de Goede2015-08-31-0/+8
| | | | | | | | | | We are using dma, so we should flush the cache before starting the dma, and invalidate it once the dma is done. Things are working without this by mostly luck, but lets not rely on that. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Turn off clocks when we're done with the nandHans de Goede2015-08-31-2/+15
| | | | | | | | | | | | Turn off the nand and dma clocks when we're done with the nand, this puts the nand and dma controllers back into a clean state for when the kernel boots. Without this the kernel will not boot properly when it is built with dma-controller support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessaryHans de Goede2015-08-31-0/+3
| | | | | | | | Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are actually using the nand. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Do not bother writing the spare-area reg in syndrome modeHans de Goede2015-08-31-4/+1
| | | | | | | | | | | | In syndrome mode we set the NFC_SEQ bit in the command register, so the spare-area register is not used. Also the value currently being written is actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE" not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE. So the current code only serves to confuse the user -> remove it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: We only need to reset the nand chip onceHans de Goede2015-08-31-10/+10
| | | | | | | There is no need to reset the nand chip for every ecc-block read. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Drop unnecessary temp bufHans de Goede2015-08-31-27/+8
| | | | | | | | | | | | | | | | | nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE or spl_image.load_addr as destination, both of which are properly aligened, and have plenty of space for "overshooting" up to CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks. This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in SPL size, which is a lot on the total 24k we have. Note this changes the dma destination from SRAM to DRAM, so this patch updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mtd: denali_spl: do not allocate page_buffer in .bss sectionMasahiro Yamada2015-08-30-20/+12
| | | | | | | | | | | | | | | | | | | Since commit 2580a2a7e719 ("mtd: nand: Increase max sizes of OOB and Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build with the following error message: arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer as static data: static uint8_t page_buffer[NAND_MAX_PAGESIZE]; This buffer required 8KB in .bss section before that commit and now it has been increased to 16KB. Given limited code/memory size for SPL, it is not a good idea to allocate a page buffer statically. In the first place, the load address 'dst' can be used as a page buffer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mtd/nand/ubi: assortment of alignment fixesMarcel Ziswiler2015-08-28-1/+1
| | | | | | | | | | | | | | Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer alignment into account which led to failures of the following form: ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Scott Wood <scottwood@freescale.com> [trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* mtd: nand: mxs invalidate dcache before DMA readPeng Fan2015-08-25-0/+6
| | | | | | | | | | | Follow linux dma flow: Before DMA read, be sure to invalidate the cache over the address range of DMA buffer to prevent cache coherency problems. After DMA read, invalidate dcache again. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
* mtd: nand: mxs support oobsize bigger than 512Peng Fan2015-08-25-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ecc chunk data size is 512 and oobsize is bigger than 512, there is a chance that block_mark_bit_offset conflicts with bch ecc area. The following graph is modified from kernel gpmi-nand.c driver with each data block 512 bytes. We can see that Block Mark conflicts with ecc area from bch view. We can enlarge the ecc chunk size to avoid this problem to those oobsize which is larger than 512. | P | |<----------------------------------------------------------------->| | | | (Block Mark) | | P' | | | | |<--------------------------------------------------->| D | | O'| | |<--------->| |<->| V V V V V +---+--------------+-+--------------+-+--------------+-+----------+-+---+ | M | data |E| data |E| data |E| data |E| | +---+--------------+-+--------------+-+--------------+-+----------+-+---+ ^ ^ | O | |<---------------->| P : the page size for BCH module. E : The ECC strength. G : the length of Galois Field. N : The chunk count of per page. M : the metasize of per page. C : the ecc chunk size, aka the "data" above. P': the nand chip's page size. O : the nand chip's oob size. O': the free oob. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com>
* mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driverStefan Roese2015-08-25-0/+1693
| | | | | | | | | | | | | | | | | | | | | | | Cloned from the Linux driver v4.2.0-rc2. Plus some patches from Antoine Tenart enabling controller initialization and ONFI timing support: http://lists.infradead.org/pipermail/linux-mtd/2015-July/060197.html Please note that this driver needs the Linux NAND subsystem sync to v4.1 from Scott to be applied: https://www.mail-archive.com/u-boot@lists.denx.de/msg175762.html Otherwise it will not compile. Tested on the Marvell Armada XP DB-MV784MP-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Cc: Ezeguil Garcia <ezequiel.garcia@free-electrons.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Scott Wood <scottwood@freescale.com>
* nand: Sync with Linux v4.1Scott Wood2015-08-25-193/+573
| | | | | | | | | | | Update the NAND code to match Linux v4.1. The previous sync was from Linux v3.15 in commit 4e67c57125290b25. CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented and not selected by any board. Signed-off-by: Scott Wood <scottwood@freescale.com>
* mtd: Introduce mtd_block_isreserved()Ezequiel Garcia2015-08-25-2/+53
| | | | | | | | | | | | | | | | In addition to mtd_block_isbad(), which checks if a block is bad or reserved, it's needed to check if a block is reserved only (but not bad). This commit adds an MTD interface for it, in a similar fashion to mtd_block_isbad(). While here, fix mtd_block_isbad() so the out-of-bounds checking is done before the callback check. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Pekon Gupta <pekon@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> [scottwood: Cherry-picked from Linux 8471bb73ba10ed67] Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand: Remove __UBOOT__ ifdefsScott Wood2015-08-25-428/+4
| | | | | | | I didn't approve the patch that added them. Get them out of the way before doing a sync. Signed-off-by: Scott Wood <scottwood@freescale.com>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* nand: lpc32xx: add ECC layout for small page NANDSylvain Lemieux2015-08-18-1/+17
| | | | | | | | | | Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (ECC layout for small page) This layout is matching the lpc32xx NAND SLC Linux Kernel driver. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* nand: lpc32xx: add hardware ECC supportSylvain Lemieux2015-08-18-4/+409
| | | | | | | | | | | | Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (hardware ECC support) - lpc3250 header file missing SLC NAND registers definition The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* sf: ops: Add spi_flash_copy_mmap functionTom Rini2015-08-17-1/+7
| | | | | | | | | | When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* sf: Make 4K sector support configurableMarek Vasut2015-08-17-0/+19
| | | | | | | | | | | | | | | | Make the support for 4K subpage I/O on a SPI NOR flash configurable. A board which requires the SPI NOR to be accessed in larger 32KiB or 64KiB pages can disable the 4K subpage support, but by default, the support for 4K subpage I/O is enabled. The functionality of this option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux. This is extremely useful in case one uses UBI on a SPI NOR flash. UBI needs at least 15k EBs and can not work on a flash which uses 4k ones, so disabling the support for 4k subpages lets UBI work on such flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* tegra: nand: disable subpage writesMarcel Ziswiler2015-08-13-0/+3
| | | | | | | | Disable subpage writes as we do not provide ecc->hwctl. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mtd/nand/tegra: alignment workaroundMarcel Ziswiler2015-08-13-51/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Integrate cache alignment bounce buffer to workaround issues as follows: Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)... ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Done Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ] Starting kernel ... undefined instruction pc : [<005ff03c>] lr : [<0000800c>] sp : 0144b6e8 ip : 01000188 fp : 0144a6c8 r10: 00000000 r9 : 411fc090 r8 : 00000100 r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000 r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: fix read_byte required for proper onfi detectionMarcel Ziswiler2015-08-13-31/+7
| | | | | | | | | | | | | | | | | | Fix PIO read_byte() implementation not only used for the legacy READ ID but also the PARAM command required for proper ONFI detection. This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late (not mainline yet but getting there soon I hope). I vaguely remember that those commands are special on 16-bit bus NAND (e.g. always return 8-bit data regardless) and later Linux MTD fixed/ changed the way this is handled which in turn broke once U-Boot pulled that in. Basically instead of doing PIO read regular DMA block read is now used which this patch actually fixes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* nand: lpc32xx: add SLC NAND controller supportVladimir Zapolskiy2015-08-12-0/+177
| | | | | | | | | | | | | | | | | | | | | The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* spl: nand: simple: replace readb() with chip specific read_buf()Vladimir Zapolskiy2015-08-12-2/+5
| | | | | | | | | | | | | | | Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework. NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
* nand, atmel: remove udelay in spl_nand_erase_one()Heiko Schocher2015-08-12-2/+0
| | | | | | | | remove unneeded udelay() in this function, as we use the dev_ready pin. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* sunxi: nand: Add board configuration optionsPiotr Zierhoffer2015-08-08-0/+40
| | | | | | | | | | | | | | | When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND. This commit also introduces the configurable options in Kconfig. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: nand: Add basic sunxi NAND driver for SPL with DMA supportPiotr Zierhoffer2015-08-08-0/+354
| | | | | | | | | | | | | This driver adds NAND support to SPL. It was tested on Allwinner A20. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sf: kconfig: add kconfig options for spi flashesNikita Kiryanov2015-08-02-0/+44
| | | | | | | | | | Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig. Cc: Jagan Teki <jteki@openedev.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* mtd: fix false positive "Offset exceeds device limit" errorMasahiro Yamada2015-07-10-2/+3
| | | | | | | | | | | | | | | | | | | | | | Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* sf: Kconfig: Add SPI_FLASH_BAR entryJagan Teki2015-07-01-0/+8
| | | | | | Added SPI_FLASH_BAR entry on Kconfig with help description Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Kconfig: Add SPI_FLASH_DATAFLASH entryJagan Teki2015-07-01-10/+15
| | | | | | | | | | | Added SPI_FLASH_DATAFLASH entry on Kconfig with help description. data flash driver comes with good decription, hence moved the same on to kconfig help decription. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Haikun Wang <haikun.wang@freescale.com>
* sf: Kconfig: Add SPI_FLASH_MTD entryJagan Teki2015-07-01-0/+12
| | | | | | | | Added SPI_FLASH_MTD entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Heiko Schocher <hs@denx.de>
* sf: Kconfig: Update SPI_FLASH entryJagan Teki2015-07-01-9/+9
| | | | | | | Updated SPI_FLASH entry on Kconfig with depends on and along with config help description. Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Add Kconfig menu entryJagan Teki2015-07-01-0/+4
| | | | | | Added Kconfig menu ... endmenu enties for spi flash suppor Signed-off-by: Jagan Teki <jteki@openedev.com>
generated by cgit v1.1 at 2024-11-15 00:41:58 +0000