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* reset: Drop the reset failure messageSimon Glass2016-05-26-1/+1
| | | | | | This adds to code size and is not needed, since hang() will print a message. Signed-off-by: Simon Glass <sjg@chromium.org>
* Rename reset to sysresetStephen Warren2016-05-26-123/+124
| | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-23-0/+206
| | | | | | | | Loading ACPI table from QEMU's fw_cfg interface is not x86 specific (ARM64 may also make use of it). So move the code to common place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-23-3/+3
| | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-23-17/+13
| | | | | | | | | | | The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-23-0/+191
| | | | | | | | | | | | This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-03-14-3/+1
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| * dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-3/+1
| | | | | | | | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* superio: Add SMSC SIO1007 driverBin Meng2016-02-21-0/+127
| | | | | | | | | | | The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management. This adds a simple driver to enable serial port and handle GPIO. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* misc: Add simple driver to enable the legacy UART on Winbond Super IO chipsStefan Roese2016-01-28-0/+50
| | | | | | | | | | | On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cros_ec: Disable the Chrome OS EC in SPLSimon Glass2016-01-21-0/+2
| | | | | | | This is not used in SPL so don't allow it to be built there, even if I2C is enabled in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add a power sequencing uclassSimon Glass2016-01-21-0/+43
| | | | | | | | Some devices need special sequences to be used when starting up. Add a uclass for this. Drivers can be added to provide specific features as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-25/+2
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* Move console definitions into a new console.h fileSimon Glass2015-11-19-1/+1
| | | | | | | | The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: cros_ec: fix uninitialized use of lenDaniel Schwierzeck2015-11-19-0/+1
| | | | | | | | | | | | | | | | Building with gcc-5.2 raises this warning: drivers/misc/cros_ec_sandbox.c: In function cros_ec_sandbox_packet: drivers/misc/cros_ec_sandbox.c:483:5: warning: len may be used uninitialized in this function [-Wmaybe-uninitialized] if (len < 0) ^ If the function process_cmd() is called with req_hdr->command == EC_CMD_ENTERING_MODE, the value of len will be returned uninitialized. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* cros_ec: Use udevice instead of cros_ec_dev for keyboard functionsSimon Glass2015-11-19-5/+9
| | | | | | | In preparation for converting the cros_ec keyboard driver to driver model, adjust the cros_ec functions it will use to use a normal struct udevice. Signed-off-by: Simon Glass <sjg@chromium.org>
* altera_sysid: change ioremap to map_physmemThomas Chou2015-11-18-2/+3
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* Merge git://git.denx.de/u-bootStefano Babic2015-11-12-3/+2
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| * misc: altera_sysid: minor clean upThomas Chou2015-11-06-2/+2
| | | | | | | | | | | | | | - Remove the penultimate comma in of_match ids Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-30-1/+0
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| | * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | driver: misc: add MXC_OCOTP Kconfig entryPeng Fan2015-10-30-0/+7
|/ / | | | | | | | | | | | | | | | | Add MXC_OCOTP Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-10-27-2/+2
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| * dm: Rename dev_get_parentdata() to dev_get_parent_priv()Simon Glass2015-10-23-2/+2
| | | | | | | | | | | | | | | | The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | allow LED initialization without STATUS_LED_BOOTBernhard Nortmann2015-10-24-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For current U-Boot to initialize status LEDs via status_led_init(), it is required to have both CONFIG_STATUS_LED and STATUS_LED_BOOT defined. This may be a particular concern with GPIO LEDs, where __led_init() is required to correctly set up the GPIO (gpio_request and gpio_direction_output). Without STATUS_LED_BOOT the initialization isn't called, which could leave the user with a non-functional "led" command - due to the fact that the LED routines in gpio_led.c use gpio_set_value() just fine, but the GPIO never got set up properly in the first place. I think having CONFIG_STATUS_LED is sufficient to justify a corresponding call to status_led_init(), even with no STATUS_LED_BOOT defined. To do so, common/board_r.c needs call that routine, so it now is exposed via status_led.h. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> [trini: Add dummy __led_init to pca9551_led.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* | add generic stubs for GPIO LEDsBernhard Nortmann2015-10-23-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For boards that support LEDs driven via GPIO (CONFIG_GPIO_LED), it may be useful to have some generic stubs (wrapper functions) for the "colored" LEDs. This allows defining STATUS_LED_* values directly to GPIO numbers, e.g.: #define STATUS_LED_GREEN 248 /* = PH24 */ To keep those optional, it's probably best to introduce an additional configuration setting. I've chosen CONFIG_GPIO_LED_STUBS for that. Placing the code in drivers/misc/gpio_led.c also ensures that it automatically depends on CONFIG_GPIO_LED too. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | nios2: convert altera sysid to driver modelThomas Chou2015-10-23-0/+109
| | | | | | | | | | | | | | | | Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dm: implement a Miscellaneous uclassThomas Chou2015-10-23-0/+61
|/ | | | | | | | | Implement a Miscellaneous uclass with generic read or write operations. This class is used only for those do not fit other more general classes. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* sandbox: Correct operaion of 'reset' commandSimon Glass2015-10-05-1/+1
| | | | | | | | | | | | | | Currently 'reset' only works with the test device tree. When run without a device tree, or with the normal device tree, the following error is displayed: Reset not supported on this platform Fix the driver and the standard device tree to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
* driver: misc: correct Kconfig entryPeng Fan2015-09-11-1/+1
| | | | | | | | | | | | | Should use FSL_SEC_MON, not CONFIG_FSL_SEC_MON as Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-02-6/+147
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| * mxc: ocotp fix hole in shadow registersPeng Fan2015-09-02-5/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * imx: ocotp: mxc add i.MX7D supportAdrian Alonso2015-09-02-1/+73
| | | | | | | | | | | | | | | | | | * Ocotp of i.MX7D has different operation rule. This patch is to add support for i.MX7D ocotp. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * mxs_ocotp: Shift the HBUS divider correctlyChris Smith2015-09-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk() for the purpose or restoring it back later, the value is not shifted by the HBUS divider offset in that register. This is not a problem, since the shift is zero on all MXS hardware. Add the shift anyway, for completeness and in case FSL ever decides to re-use this driver on future designs. Signed-off-by: Chris Smith <chris@zxdesign.info> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | arm/ls102xa:add hwconfig setting to support disable unused devicesZhuoyu Zhang2015-09-01-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | driver: misc: debug server: Update Error messagePrabhakar Kushwaha2015-09-01-5/+5
|/ | | | | | | | Append "debug server FW" in error message to make more informative. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* x86: superio: Add keyboard controller support to smsc_lpc47m driverBin Meng2015-08-26-1/+12
| | | | | | | | | Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: hierarchize drivers Kconfig menuMasahiro Yamada2015-08-12-0/+8
| | | | | | | | | | | The menuconfig for drivers are getting more and more cluttered and unreadable because too many entries are displayed in a single flat menu. Use hierarchic menu for each category. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Update to apply again in a few places, drop USB hunk] Signed-off-by: Tom Rini <trini@konsulko.com>
* cros_ec: Remove the old tunnel codeSimon Glass2015-08-05-267/+1
| | | | | | This is not needed with driver mode. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: Support the LDO access method used by springSimon Glass2015-08-05-10/+11
| | | | | | | | | | | | | | | | | | | | | | | Add a driver to support the special LDO access used by spring. This is a custom method in the cros_ec protocol - it does not use an I2C pass-through. There are two implementation choices: 1. Write a special LDO driver which can talk across the EC. Duplicate all the logic from TPS65090 for retrying when the LDO fails to come up. 2. Write a special I2C bus driver which pretends to be a TPS65090 and transfers reads and writes using the LDO message. Either is distasteful. The latter method is chosen since it results in less code duplication and a fairly simple (30-line) implementation of the core logic. The crosec 'ldo' subcommand could be removed (since i2c md/mw will work instead) but is retained as a convenience. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: cros_ec: Convert the I2C tunnel code to use driver modelSimon Glass2015-08-05-5/+88
| | | | | | | | | | | | | | | | | | | The Chrome OS EC supports tunnelling through to an I2C bus on the EC. This currently uses a copy of the I2C command code and a special 'crosec' sub-command. With driver model we can define an I2C bus which tunnels through to the EC, and use the normal 'i2c' command to access it. This simplifies the code and removes some duplication. Add an I2C driver which tunnels through to the EC. Adjust the EC code to support binding child devices so that it can be set up. Adjust the existing I2C xfer function to fit driver model better. For now the old code remains to allow things to still work. It will be removed in a later patch once the new flow is fully enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* misc: led: pca9551_led: Fix problem with multiple blink frequenciesStefan Roese2015-07-27-10/+22
| | | | | | | | | | | Only 2 frequencies are supported. The current driver implementation does not always use the 2 last configured blink frequencies. This patch fixes this problem. So that the last two entered frequencies are active. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Tom Rini <trini@konsulko.com>
* dm: test: Add a test for the system controller uclassSimon Glass2015-07-21-0/+28
| | | | | | | Add a test to confirm that we can access system controllers and find their driver data. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Use the reset driver to handle resetSimon Glass2015-07-21-1/+1
| | | | | | | Move sandbox over to use the reset uclass for reset, instead of a direct call to do_reset(). This allows us to add tests. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add a warm and cold reset driverSimon Glass2015-07-21-0/+101
| | | | | | | | Add drivers for sandbox. One can only perform a warm reset (which does nothing). The other can perform a cold reset or a power reset (the latter will quit U-Boot). These can be used for testing the reset uclass. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: reset: Allow reset_walk() to returnSimon Glass2015-07-21-6/+25
| | | | | | | | | | Add a new reset_walk_halt() function to cause a reset and then halt on failure. The reset_walk() function returns an error code. This is needed for testing since otherwise U-Boot will halt in the middle of a test. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add a system reset uclassSimon Glass2015-07-21-0/+72
| | | | | | | | | | | | | | | | It is common for system reset to be available at multiple levels in modern hardware. For example, an SoC may provide a reset option, and a board may provide its own reset for reasons of security or thoroughness. It is useful to be able to model this hardware without hard-coding the behaviour in the SoC or board. Also there is a distinction sometimes between resetting just the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting power. To achieve this, add a simple system reset uclass. It allows multiple devices to provide reset functionality and provides a way to walk through them, requesting a particular reset type until is it provided. Signed-off-by: Simon Glass <sjg@chromium.org>
* driver/fsl_debug_server: Fix the DDR hide logic for LS2085aBhupesh Sharma2015-07-20-0/+5
| | | | | | | | | | This patch fixes the DDR hide logic for LS2085a, correcting the way the Debug Server FW and MC FW images are placed on the top of system DDR and how the rest of the system DDR space is made visibile to Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* sandbox: cros_ec: Support EC_CMD_ENTERING_MODE emulationSimon Glass2015-05-14-0/+2
| | | | | | Emualate this function which is used with Chrome OS verified boot. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-06 02:36:25 +0000