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authorChris Smith <chris@zxdesign.info>2015-07-12 15:00:11 +0200
committerStefano Babic <sbabic@denx.de>2015-09-02 15:26:13 +0200
commitd4b8b5d46effb22f9735b924a7da502c2907b82b (patch)
treef7371cd912c5d61e23b9e4e76352a7298316d9e4 /drivers/misc
parentf3488bb39d0ffe274cefdc7c42e3e63a636d9cd6 (diff)
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mxs_ocotp: Shift the HBUS divider correctly
When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk() for the purpose or restoring it back later, the value is not shifted by the HBUS divider offset in that register. This is not a problem, since the shift is zero on all MXS hardware. Add the shift anyway, for completeness and in case FSL ever decides to re-use this driver on future designs. Signed-off-by: Chris Smith <chris@zxdesign.info> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers/misc')
-rw-r--r--drivers/misc/mxs_ocotp.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c
index 6f0a1d3..6c0d247 100644
--- a/drivers/misc/mxs_ocotp.c
+++ b/drivers/misc/mxs_ocotp.c
@@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val)
/* Return the original HCLK clock speed. */
*val = readl(&clkctrl_regs->hw_clkctrl_hbus);
*val &= CLKCTRL_HBUS_DIV_MASK;
+ *val >>= CLKCTRL_HBUS_DIV_OFFSET;
/* Scale the HCLK to 454/19 = 23.9 MHz . */
scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET;