summaryrefslogtreecommitdiff
path: root/drivers/misc
Commit message (Collapse)AuthorAgeLines
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-1/+12
|\ | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| * arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-1/+12
| | | | | | | | | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT nodeSimon Glass2013-12-09-2/+1
| | | | | | | | | | | | | | This allows us to put the SPI flash chip inside the SPI interface node, with U-Boot finding the correct bus and chip select automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-12-02-0/+165
|\ \
| * | Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-0/+141
| |/ | | | | | | | | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
* | gpio_led: add support for inverted polarityIgor Grinberg2013-11-25-2/+25
| | | | | | | | | | | | | | | | | | | | Some GPIO connected LEDs have inverted polarity. Introduce new config option: CONFIG_GPIO_LED_INVERTED_TABLE for the specifying the inverted GPIO LEDs list and add support for this in the gpio_led driver. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Tested-by: Ilya Ledvich <ilya@compulab.co.il>
* | gpio_led: check gpio_request() return valueIgor Grinberg2013-11-25-1/+5
|/ | | | | | | | | Add a check for the gpio_request() function return value and do not try to configure the GPIO if the gpio_request() call fails. Also, print an error message indicating the gpio_request() has failed. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Tested-by: Ilya Ledvich <ilya@compulab.co.il>
* drivers: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-37/+15
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-211/+13
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* cros: add LPC support for cros_ecHung-ying Tyan2013-06-26-0/+284
| | | | | | | | | | This patch adds LPC support for carrying out the cros_ec protocol. Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* cros: exynos: add SPI support for cros_ecHung-ying Tyan2013-06-26-0/+162
| | | | | | | | | This patch adds SPI support for carrying out the cros_ec protocol. Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* cros: add I2C support for cros_ecHung-ying Tyan2013-06-26-0/+200
| | | | | | | | | | This patch adds I2C support for carrying out the cros_ec protocol. Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* cros: add cros_ec driverHung-ying Tyan2013-06-26-0/+1305
| | | | | | | | | | | | | | | | | | | This patch adds the cros_ec driver that implements the protocol for communicating with Google's ChromeOS embedded controller. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-2/+2
|\
| * twl4030: make twl4030_i2c_write_u8 prototype consistentNishanth Menon2013-05-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | u-boot standard i2c register write prototype is i2c_reg_write(u8 addr, u8 reg, u8 val) twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val) Signed-off-by: Nishanth Menon <nm@ti.com>
* | Add mxc_ocotp driverBenoît Thébaudeau2013-04-28-0/+217
| | | | | | | | | | | | Add an mxc_ocotp driver for i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | Add fsl_iim driverBenoît Thébaudeau2013-04-28-0/+287
|/ | | | | | Add a fsl_iim driver common to i.MX and MPC. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* x86: Add console command to display CBMEM console bufferVadim Bendebury2012-11-30-0/+67
| | | | | | | | | | This command is useful to allow to observe messages generated by coreboot and u-boot until present. In particular it is handy when u-boot is instrumented to fall through into console mode on startup errors. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add CBMEM console driver for corebootVadim Bendebury2012-11-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds upon the recently introduced CBMEM console feature of coreboot. CBMEM console uses a memry area allocated by coreboot to store the console output. The memory area has a certain structure, which allows to determine where the buffer is, the buffer size and the location of the pointer in the buffer. This allows different phases of the firmware (rom based coreboot, ram based coreboot, u-boot after relocation with this change) to keep adding text to the same buffer. Note that this patch introduces a new console driver and adds the driver to the list of drivers to be used for console output, i.e. it engages only after u-boot relocates. Usiong CBMEM console for capturing the pre-relocation console output will be done under a separate change. >From Linux, run the cbmem.py utility (which is a part of the coreboot package) to see the output, e.g.: vvvvvvvvvvvvvvvvv SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode flags: 64bit ilck stag led pmp pio ... Magic signature found Kernel command line: "cros_secure quiet loglevel=1 console=tty2... ^^^^^^^^^^^^^^^^^ Note that the entire u-boot output fits into the buffer only if the coreboot log level is reduced from the most verbose. Ether the buffer size will have to be increased, or the coreboot verbosity permanently reduced. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxxScott Wood2012-11-26-334/+0
| | | | | | | | | | | It's arch code and not a driver, so move it where it belongs. When it originally went into drivers/misc there was no 8xxx CPU directory. This will make new-SPL support a little easier since we can keep the CPU stuff together and not need to pull stuff in from drivers/misc. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
* pmic: Move pmic related code to ./drivers/power directoryŁukasz Majewski2012-11-14-658/+0
| | | | | | | | The PMIC framework has been moved to its more natural place ./drivers/power from ./drivers/misc directory. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* pmic: Extend PMIC framework to support multiple instances of PMIC devicesŁukasz Majewski2012-11-14-51/+135
| | | | | | | | | | | | | | | | | | The PMIC framework has been extended to support multiple instances of the variety of devices responsible for power management. This change allows supporting of e.g. fuel gauge, charger, MUIC (Micro USB Interface Circuit). Power related includes have been moved to ./include/power directory. This is a first of a series of patches - in the future "pmic" will be replaced with "power". Two important issues: 1. The PMIC needs to be initialized just after malloc is configured 2. It uses list to hold information about available PMIC devices Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
* pmic:max8997: Switch the MAX8997 PMIC to be used with multibus I2CŁukasz Majewski2012-11-14-1/+2
| | | | | | | | PMIC MAX8997 is now ready to work with single and multibus soft I2C implementation. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* pmic:i2c: Add I2C sensor byte order (big/little) to PMIC frameworkŁukasz Majewski2012-11-14-9/+29
| | | | | | | | | | | | | Since the pmic_reg_read is the u32 value, the order in which bytes are placed to form u32 value is important. Support for big and little sensor endianess is added. Moreover calls to [leXX|beXX]_to_cpu have been added to support little and big endian SoCs. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* pmic:i2c: Handle PMIC I2C transmission comprising of two bytesŁukasz Majewski2012-11-14-1/+8
| | | | | | | | | This patch adds support for proper handling of a PMIC I2C transmission comprising of two bytes. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
* powerpc/corenet_ds: Slave module for boot from PCIELiu Gang2012-08-23-6/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE interface. For the corenet platform, ucode is for Fman. NOTE: Because the slave can not erase, write master's NOR flash by PCIE interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Put the slave's ucode and ENV into it's own memory space. 4. Normally boot from local NOR flash. 5. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the slave module, need to finish these processes: 1. Set the boot location to one PCIE interface by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID of one PCIE for the boot. 4. Set a specific TLB entry in order to fetch ucode and ENV from master. 5. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 6. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. In addition, the processes are very similar between boot from SRIO and boot from PCIE. Some configurations like the address spaces can be set to the same. So the module of boot from PCIE was added based on the existing module of boot from SRIO, and the following changes were needed: 1. Updated the README.srio-boot-corenet to add descriptions about boot from PCIE, and change the name to README.srio-pcie-boot-corenet. 2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to "xxxx_SRIO_PCIE_BOOT", and the image builded with "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and from PCIE. 3. Updated other macros and documents if needed to add information about boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-0/+27
| | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* pmic: dialog: Avoid name conflictsFabio Estevam2012-05-15-2/+2
| | | | | | | | | | As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC, we need to be able to build both drivers. Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* pmic: Add support for the Dialog DA9053 PMICFabio Estevam2012-05-15-0/+38
| | | | | | Add support for the Dialog DA9053 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* misc:pmic:max8997 MAX8997 support for PMIC driverŁukasz Majewski2012-05-15-0/+44
| | | | | | | | This commit adds support for MAX8997 PMIC driver. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Stefano Babic <sbabic@denx.de>
* pmic_i2c: Return error in case of invalid pmic_i2c_tx_numFabio Estevam2012-03-27-0/+6
| | | | | | | | | Return error in case of invalid pmic_i2c_tx_num. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Stefano Babic <sbabic@denx.de>
* misc: pmic: fix regression in pmic_fsl.c (SPI)Helmut Raiger2011-11-03-6/+2
| | | | | | | | | This fixes write access to PMIC registers, the bug was introduced partly in commit 64aac65099 and in commit c9fe76dd91. It was tested on an i.mx31 with a mc13783. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Stefano Babic <sbabic@denx.de>
* misc: pmic: drop old Freescale's pmic driverStefano Babic2011-10-27-236/+0
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* misc: pmic: addI2C support to pmic_fsl driverStefano Babic2011-10-27-4/+13
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* misc: pmic: use I2C_SET_BUS in pmic I2CStefano Babic2011-10-27-1/+1
| | | | | | | | Instead of using directly the i2c_set_bus() function, the I2C_SET_BUS macro must be used to avoid build errors for targets without multibus I2C. Signed-off-by: Stefano Babic <sbabic@denx.de>
* misc: pmic: Freescale PMIC switches to generic PMIC driverStefano Babic2011-10-27-0/+58
| | | | | | Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
* misc:pmic:max8998 MAX8998 support at a new PMIC driver.Łukasz Majewski2011-10-27-0/+44
| | | | | | | | This commit adds support for MAX8998 PMIC driver. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
* misc:pmic:core New generic PMIC driverŁukasz Majewski2011-10-27-0/+351
| | | | | | | | | | | | | | I2C or SPI PMIC devices can be accessed. Separate files: pmic_i2c.c and pmic_spi.c are responsible for handling transmission over I2C or SPI bus. New flags: CONFIG_PMIC - enable PMIC general device. CONFIG_PMIC_I2C/SPI - specify the interface to be used. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
* cosmetic: fsl_pmic: cosmetic for the help messageJason Liu2011-09-30-1/+1
| | | | | | | | | | | | This is cosmetic patch for the help message: Before: pmic dump [numregs] dump registers After: pmic dump [numregs] - dump registers Signed-off-by: Jason Liu <jason.hui@linaro.org> Acked-by: Stefano Babic <sbabic@denx.de>
* Convert ISO-8859 files to UTF-8Albert ARIBAUD2011-08-04-1/+1
| | | | | | | | There was a mix of UTF-8 and ISO-8859 files in the U-Boot source tree, which could cause issues with the patchwork review system. This commit converts all ISO-8859 files to UTF-8. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Minor coding style cleanup.Wolfgang Denk2011-05-19-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc/8xxx: Fix LAW init to respect pre-initialized entriesKumar Gala2011-04-04-0/+20
| | | | | | | | | | If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW entries consider them good and mark them used. In the NAND SPL case we skip re-initializing based on the law_table since the SPL phase already did that. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law: Fix LAW printing functionKumar Gala2011-02-22-1/+1
| | | | | | | | | | | | | We had an extra '0x' in the output of the LAWAR header that would cause output like: LAWBAR11: 0x00000000 LAWAR0x11: 0x80f0001d intead of: LAWBAR11: 0x00000000 LAWAR11: 0x80f0001d Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add basic support for Freescale's mc9sdz60Stefano Babic2011-02-02-2/+54
| | | | | | | | The patch adds helper funtions for basic access to the registers of the MC9sdz60 chip (multifunctional device with RTC and CAN) via I2C interface. Signed-off-by: Stefano Babic <sbabic@denx.de>
* fsl_pmic: add I2C interface supportLiu Hui-R643432011-02-02-5/+40
| | | | | | This patch add I2C interface for fsl_pmic driver support Signed-off-by: Jason Liu <r64343@freescale.com>
* powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headersKumar Gala2011-01-19-21/+1
| | | | | | | | | | | Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/p2040: Add various p2040 specific informationKumar Gala2011-01-19-2/+2
| | | | | | | | | | Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1014 ProcessorPoonam Aggrwal2011-01-19-1/+1
| | | | | | | | | | | | The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1010 ProcessorPoonam Aggrwal2011-01-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-05 17:08:56 +0000