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* Fix spelling of "occurred".Vagrant Cascadian2016-05-02-2/+2
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* ddr: altera: Repair DQ window centering codeMarek Vasut2016-04-20-8/+7
| | | | | | | | | | | | The code uses a lot of signed numbers, which ended up in variables of unsigned type, which resulted in all sorts of underflows. This in turn caused incorrect calibration on certain boards. Moreover, repair the readout of the DQ delay, which was being pulled from wrong register. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Staticize global variablesMarek Vasut2016-04-20-4/+4
| | | | | | | | | Just staticize global variables in sequencer, since there is no point in having these symbols available outside of the DDR code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut2016-04-20-66/+66
| | | | | | | | | | | | Originally, the DLEVEL selects the debug level within the sequencer code, but only displays the messages on that particular debug level. Tweak the handling such that for particular debug level, debug messages on that level and lower are displayed. This allows better regulation of debug message verbosity. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut2016-04-20-3/+13
| | | | | | | | | This one last set of delay configuration registers was not properly zeroed out originally, fix it and zero them out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Remove unnecessary ODT mode configMarek Vasut2016-04-20-1/+0
| | | | | | | | | | | There is no point in resetting the ODT setting if the write test failed, since the code will always retry the calibration and thus reconfigure the ODT anyway OR the code will fail calibration and halt. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Remove unnecessary update of the SCCMarek Vasut2016-04-20-1/+0
| | | | | | | | | | | Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is followed by SCC manager update. Moreover, only this function triggers the SCC manager update internally. Thus, remove the internal invocation to avoid triggering the update twice. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Fix DRAM end value in protection ruleMarek Vasut2016-04-20-1/+1
| | | | | | | | | | The hi address bitfield in the protection rule must be set to the last address in the region which the rule represents. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut2016-04-20-1/+1
| | | | | | | | | | The code should be setting registers to zero, not one register to value. Swap the order of arguments to correct the behavior. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Tweak DQS tracking enable handlingMarek Vasut2016-04-20-2/+5
| | | | | | | | | | In the most unlikely case the DQS tracking was to be disabled, make sure we do not errornously re-enable it. Note that DQS tracking is enabled on all systems observed thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* ddr: altera: Replace ad-hoc constant with macroMarek Vasut2016-04-20-2/+2
| | | | | | | | | The bit 22 is in fact DQS tracking enable bit (dqstrken) and there is a macro for this bit already, so use it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* Fix typo choosen in comments and printf logsAlexander Merkle2016-03-27-2/+2
| | | | | | | | Minor change: chosen is written with one "o". No code change here, only comment & printf. Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: mvebu: Fix ddr3_init() cpu configDirk Eibach2016-03-24-2/+0
| | | | | | | | Armada 38x has a maximum of two cores. Probably copy/paste bug from Armada XP. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-21-5/+39
| | | | | | | | | During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu2016-03-21-7/+63
| | | | | | | | | | Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-1/+1
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+497
| | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout2016-01-25-0/+1
| | | | | | | | Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-25-0/+10
| | | | | | | | | | | | Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-25-0/+18
| | | | | | | | | | | | During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-30/+10
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* ddr: altera: Init the rule ID in debug codeMarek Vasut2016-01-16-0/+1
| | | | | | | | | | Init the rule ID, otherwise the debug code will always dump the protection settings entry 0. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com>
* mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter2016-01-14-11/+11
| | | | | | | | | This should make it clear that this symbol is meant to be defined by board headers. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* axp: Fix debugging support in DDR3 write levelingPhil Sutter2016-01-14-2/+2
| | | | | | | | | | If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing. In addition to that, get rid of debug output printing non-existent counter variable. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2016-01-14-0/+8
| | | | | | | | | | | Currently, ECC support is enabled for all Armada XP boards. So the DDR3 driver tries to configure the controller with ECC support, even on boards without ECC. This patch makes this ECC optional which now can be configured on a board-per-board basis. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-14-17/+0
| | | | | | | | | | | | | | | | | | gcc 5.1 generates this new warning (for Armada 38x platforms): drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result': drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument] memcpy(result, training_result, sizeof(result)); ^ drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) ^ Since this functions is not referenced anywhere, lets just remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-15-34/+0
| | | | | | | | As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-13-3/+6
| | | | | | | | | DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Update timing config for heavy loadYork Sun2015-12-13-2/+24
| | | | | | | In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun2015-12-13-7/+15
| | | | | | | The workaround requires different setting for range 1 vs 2. Also adjust timeout value for waiting for controller to be idle. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Update MR5 RTT parkYork Sun2015-12-13-4/+15
| | | | | | For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun2015-12-13-0/+3
| | | | | | MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Update DDR4 RTT valuesYork Sun2015-12-13-2/+235
| | | | | | | DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun2015-11-30-12/+12
| | | | | | | | | BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-30-0/+41
| | | | | | | | Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-2/+2
| | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-2/+2
| | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
* arm: mvebu: Fix SAR1_CPU_CORE_MASKDirk Eibach2015-11-17-5/+2
| | | | | | | | SAR1_CPU_CORE_MASK was wrong, probably copy/paste from another architecture. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: mvebu: a38x: Remove unsupported topologiesKevin Smith2015-11-17-77/+0
| | | | | | | | | | | | | | A lot of extra configuration information was left over in the Marvell serdes and DDR3 initialization code for boards that U-boot does not support. Remove this extra config information, and the concept of fixing up board topologies with information loaded from an EEPROM. If this needs to be done, it should be handled in the board file, not in core code. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-3/+1
| | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* drivers/ddr/fsl_ddr: Make SR_IE configurableJoakim Tjernlund2015-10-30-1/+1
| | | | | | | | | SR_IE(Self-refresh interrupt enable) is needed for Hardware Based Self-Refresh. Make it configurable and let board code handle the rest. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Reviewed-by: York Sun <yorksun@freescale.com>
* bitops: introduce BIT() definitionHeiko Schocher2015-09-11-2/+0
| | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* ddr: altera: Repair uninited variableMarek Vasut2015-08-23-1/+1
| | | | | | | | | | | | | Fix the following problem: drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full': drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized] if (found_passing_read && found_failing_read) ^ drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here u32 found_passing_read, found_failing_read, initial_failing_dtap; ^ Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Replace float multiplication with integer oneMarek Vasut2015-08-23-1/+1
| | | | | | | | | | | | | | | | This gem is really really rare, there was an actual float used in the Altera DDR init code, which pulled in floating point ops from the libgcc, just wow. Since we don't support floating point operations the same way Linux does not support them, replace this with an integer multiplication and division combo. This removes some 2kiB of size from the SPL as the floating point ops are no longer pulled in from libgcc. This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which does not contain the floating point bits. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-17-2/+2
| | | | | | | | | | | | This patch introduces the SDRAM scrubbing for ECC enabled board to fill/initialize the ECC bytes. This is done via the XOR engine to speed up the process. The scrubbing is a 2-stage process: 1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot 2) U-Boot scrubs the remaining SDRAM area(s) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on the DB-MV784MP-GP eval board. To really enable ECC support on this board the I2C EEPROM needs to get changed. As it saves the enabling of ECC support internally. For this the following commands can be used to enable ECC support on this board: Its recommended for first save (print) the value(s) in this EEPROM address: => i2c md 4e 0.1 2 0000: 05 00 .. To enable ECC support you need to set bit 1 in the 2nd byte: Marvell>> i2c mw 4e 1.1 02 Marvell>> i2c md 4e 0.1 2 0000: 05 02 .. To disable ECC support again, please use this command: Marvell>> i2c mw 4e 1.1 00 Marvell>> i2c md 4e 0.1 2 0000: 05 00 .. On other AXP boards, simply plugging an ECC DIMM should be enough to enable ECC support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* ddr: altera: sequencer: Clean checkpatch issuesMarek Vasut2015-08-08-71/+88
| | | | | | | | | Fix most of the dangling checkpatch issues, no functional change. There are still 7 warnings, 1 checks , but those are left in place for the sake of readability of the code. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Clean data typesMarek Vasut2015-08-08-48/+48
| | | | | | | Replace uintNN_t with uNN. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Pluck out misc macros from codeMarek Vasut2015-08-08-22/+15
| | | | | | | | | | | | | Actually convert the sequencer code to use socfpga_sdram_misc_config instead of the various macros. This is just an sed exercise here, no manual coding needed. This patch actually removes the need to include any board-specific files in sequencer.c , so sequencer.c namespace is now no longer poluted by QTS-generated macros. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VALMarek Vasut2015-08-08-49/+4
| | | | | | | | | This is another macro used to obfuscate the real code. The T(INIT|RESET)_CNTR._VAL is always defined, so this indirection is unnecessary. Get rid of this. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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