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* ppc/8xxx: Misc DDR related fixesKumar Gala2009-09-15-5/+5
| | | | | | | * Fix setting of ESDMODE (MR1) register - the bit shifting was wrong * Fix the format string to match size in a debug print Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-23/+0
| | | | | | | | The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala2009-06-12-2/+1
| | | | | | | | | | | | | | | The ddr code computes most things as 64-bit quantities and had some places in the middle that it was using phy_addr_t and phys_size_t. Instead we use unsigned long long through out and only at the last stage of setting the LAWs and reporting the amount of memory to the board code do we truncate down to what we can cover via phys_size_t. This has the added benefit that the DDR controller itself is always setup the same way regardless of how much memory we have. Its only the LAW setup that limits what is visible to the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-30-36/+344
| | | | | | | | | - support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
* fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu2009-03-30-1/+4
| | | | | | | | | | | | 1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com>
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+8
| | | | | | | | | | | | | Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+13
| | | | | | | | - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
| | | | | | | | According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
| | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+49
| | | | | | | | | | Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Fix compiler warning in mpc8xxx ddr codeKumar Gala2008-09-07-2/+4
| | | | | | | | | | | ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function ctrl_regs.c:523: note: 'caslat' was declared here Add a warning in DDR1 case if cas_latency isn't a value we know about. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-0/+993
The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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