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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-06-11 23:42:35 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 09:15:50 -0500 |
| commit | e7563aff174f77aa61dab1ef5d9b47bebaa43702 (patch) | |
| tree | a3ef1e9c1745d417a06328e464446436dd46f2c7 /cpu/mpc8xxx/ddr/ctrl_regs.c | |
| parent | d4b130dc80761b430dc5b410159cd158fca1a348 (diff) | |
| download | u-boot-imx-e7563aff174f77aa61dab1ef5d9b47bebaa43702.zip u-boot-imx-e7563aff174f77aa61dab1ef5d9b47bebaa43702.tar.gz u-boot-imx-e7563aff174f77aa61dab1ef5d9b47bebaa43702.tar.bz2 | |
fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT
The ddr code computes most things as 64-bit quantities and had some places
in the middle that it was using phy_addr_t and phys_size_t.
Instead we use unsigned long long through out and only at the last stage of
setting the LAWs and reporting the amount of memory to the board code do we
truncate down to what we can cover via phys_size_t.
This has the added benefit that the DDR controller itself is always setup
the same way regardless of how much memory we have. Its only the LAW
setup that limits what is visible to the system.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx/ddr/ctrl_regs.c')
| -rw-r--r-- | cpu/mpc8xxx/ddr/ctrl_regs.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 490e3dc..1689d68 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1199,8 +1199,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* Chip Select Memory Bounds (CSn_BNDS) */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - phys_size_t sa = 0; - phys_size_t ea = 0; + unsigned long long ea = 0, sa = 0; if (popts->ba_intlv_ctl && (i > 0) && ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) { |