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path: root/cpu/mpc8xxx/ddr/ctrl_regs.c
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* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-1366/+0
* fsl-ddr: Fix the turnaround timing for TIMING_CFG_4Dave Liu2010-04-07-9/+17
* fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu2010-01-05-0/+3
* fsl-ddr: add override for the Rtt_WrDave Liu2010-01-05-3/+7
* fsl-ddr: add the override for write levelingDave Liu2010-01-05-6/+14
* fsl-ddr: Fix power-down timing settingsDave Liu2010-01-05-3/+4
* ppc/8xxx: Misc DDR related fixesKumar Gala2009-09-15-5/+5
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-23/+0
* fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala2009-06-12-2/+1
* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-30-36/+344
* fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu2009-03-30-1/+4
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+8
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+13
* fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
* Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
* Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+49
* Fix compiler warning in mpc8xxx ddr codeKumar Gala2008-09-07-2/+4
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-0/+993
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