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* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-29/+29
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+4
* 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+78
* ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg2009-10-26-0/+5
* ppc/85xx: Make L2 support more robustDave Liu2009-10-26-1/+4
* relocation: Do not relocate NULL pointers.Joakim Tjernlund2009-10-08-2/+4
* 85xx: Ensure BSS segment isn't linked at address 0Peter Tyser2009-10-08-0/+11
* ppc: Enable full relocation to RAMPeter Tyser2009-10-03-1/+0
* ppc/p4080: Determine various chip frequencies on CoreNet platformsKumar Gala2009-09-24-4/+127
* ppc/p4080: Handle timebase enabling and frequency reportingKumar Gala2009-09-24-1/+22
* ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-0/+1
* ppc/p4080: CoreNet platfrom style secondary core releaseKumar Gala2009-09-24-3/+65
* ppc/p4080: CoreNet platfrom style CCSRBAR settingKumar Gala2009-09-24-18/+54
* ppc/85xx: Fix enabling of L2 cacheKumar Gala2009-09-24-3/+4
* 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQVivek Mahajan2009-09-24-3/+10
* ppc/85xx: add cpu init config file for boot from NANDMingkai Hu2009-09-24-0/+63
* ppc/85xx: add ld script file for boot from NANDMingkai Hu2009-09-24-0/+67
* ppc/85xx: Disable all async interrupt sources when we bootKumar Gala2009-09-15-0/+11
* ppc/85xx: Split out cpu_init_early into its own file for NAND_SPLKumar Gala2009-09-15-51/+77
* ppc/85xx: Change cpu_init_early_f so we can use with NAND SPLKumar Gala2009-09-15-9/+25
* ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu2009-09-15-1/+181
* ppc/85xx: Move code around to prep for NAND_SPLKumar Gala2009-09-15-23/+23
* ppc/85xx: Repack tlb_table to save spaceKumar Gala2009-09-15-4/+5
* ppc/85xx: Introduce low level write_tlb functionKumar Gala2009-09-15-14/+26
* ppc/85xx: Remove some bogus code from external interrupt handler.Scott Wood2009-09-15-8/+1
* ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.Scott Wood2009-09-15-0/+7
* ppc/85xx: Don't enable interrupts before we're readyScott Wood2009-09-15-2/+2
* ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link addressKumar Gala2009-09-09-3/+7
* ppc/85xx: Clean up do_resetKumar Gala2009-09-08-16/+9
* ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().Poonam Aggrwal2009-09-08-0/+4
* ppc/85xx/86xx: Device tree fixup for number of coresPoonam Aggrwal2009-09-08-0/+2
* ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal2009-09-08-7/+3
* ppc/85xx: Cleanup makefile and related optional filesKumar Gala2009-09-08-18/+19
* ppc/85xx: Fix bug in setup_mp codeKumar Gala2009-09-08-3/+29
* ppc/85xx: Add a simple function to search the TLBKumar Gala2009-09-08-0/+27
* 85xx: Add support for setting IVORs to fixed offset defaultsKumar Gala2009-09-08-0/+95
* ppc/85xx: Fix up eSDHC controller clock frequency in the device treeDipen Dudhat2009-09-08-0/+7
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-1/+0
* ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clkDipen Dudhat2009-09-08-1/+1
* 85xx: Improve MPIC initializationTimur Tabi2009-08-28-5/+7
* 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-1/+3
* 85xx: Add L2SRAM Register's macro definitionMingkai Hu2009-08-28-2/+3
* 85xx: Move to a common linker scriptKumar Gala2009-08-28-0/+146
* 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-1/+2
* 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-17/+39
* 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal2009-08-28-69/+1
* 85xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala2009-08-28-2/+1
* Prepare 2009.08-rc3v2009.08-rc3Wolfgang Denk2009-08-22-1/+1
* 85xx: Fix addrmap to include memoryKumar Gala2009-08-14-6/+22
* Update Freescale copyrights to remove "All Rights Reserved"Kumar Gala2009-07-29-1/+1
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