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* mp2usb: remove board supportEric BĂ©nard2011-04-11-703/+0
| | | | | | | this board was cancelled long time ago so remove it as it won't be maintained anymore Signed-off-by: Eric Bénard <eric@eukrea.com>
* ppc, mgcoge: add DIP switch detectionAndreas Huber2011-04-11-0/+18
| | | | | | | | | This reads the DIP switch on mgcoge. The DIP switch is connected to the BFTICU (0x40000089) FPGA. If the DIP switch is set the environment variable 'actual_bank' is set to 0 and starts the SW in bank0. Signed-off-by: Andreas Huber <andreas.huber@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* arm, keymile: remove unneeded codeHolger Brunck2011-04-11-7/+0
| | | | | | | | On first HW versions the BOCO FPGA was behind a MUX device. These HW versions are not supported anymore. And therefore this code can be removed, it is already unused. Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
* ea20: fix libea20.o not foundBen Gardiner2011-04-11-1/+1
| | | | | | | | | | This patch fixes ea20 after commit 6d8962e814c15807dd6ac5757904be2a02d187b8 where $(obj)lib$(BOARD).a was changed to $(obj)lib$(BOARD).o in almost all the Makefiles except ea20, probably due to merge path of the changes in 2010.12. Signed-off-by: Ben Gardiner<bengardiner@nanometrics.ca> CC: Sebastien Carlier <sebastien.carlier@gmail.com> Acked-by : Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-10-12/+56
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| * powerpc/85xx: Add PBL boot from SPI flash support on P4080DSShaohui Xie2011-04-10-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DSJiang Yutang2011-04-10-11/+45
| | | | | | | | | | | | | | | | | | | | | | For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2011-04-10-0/+16
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| * | nios2: reset cfi flash before reading envThomas Chou2011-04-08-0/+16
| |/ | | | | | | | | | | | | | | | | | | Flash might be in unknown state when u-boot is started with jtag. And got wrong env data. So reset it in board early init. We cannot use generic cfi flash routines, because flash_init() is not run yet. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* | Blackfin: bf526-ezbrd: get MAC from flashMike Frysinger2011-04-08-12/+17
| | | | | | | | | | | | The MAC address is stored in the last flash sector rather than OTP. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf518f-ezbrd: get MAC from flashMike Frysinger2011-04-08-14/+17
| | | | | | | | | | | | The MAC address is stored in the last flash sector rather than OTP. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf506f-ezkit: new board portMike Frysinger2011-04-08-0/+81
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf525-ucr2: new board portChong Huang2011-04-08-0/+70
| | | | | | | | | | | | Signed-off-by: Chong Huang <chuang@ucrobotics.com> Signed-off-by: Haitao Zhang <minipanda@linuxrobot.org> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: dnp5370: new board portAndreas Schallenberg2011-04-08-0/+158
| | | | | | | | | | | | | | | | Info about the hardware can be found here: http://www.dilnetpc.com/dnp0086.htm Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf537-pnav/blackstamp/blackvme: drop empty config.mk filesMike Frysinger2011-04-08-74/+0
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf527-sdp: update custom CFLAGS pathsMike Frysinger2011-04-08-2/+2
| | | | | | | | | | | | Looks like the filesystem shuffling missed the SDP board. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: move CONFIG_BFIN_CPU back to board config.hMike Frysinger2011-04-08-54/+0
| | | | | | | | | | | | This is a revert of 821ad16fa9900c as Wolfgang doesn't like the new code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: unify bootmode based LDR_FLAGS setupMike Frysinger2011-04-08-50/+2
| | | | | | | | | | | | Unify this convention for all Blackfin boards. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: drop CONFIG_SYS_TEXT_BASE from boardsMike Frysinger2011-04-08-84/+0
| | | | | | | | | | | | | | We don't want/use this value for Blackfin boards, so punt it and have the common code error out when people try to use it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf518f-ezbrd: don't require SPI logic all the timeMike Frysinger2011-04-08-9/+21
|/ | | | | | | Only the first run of boards had a ksz switch on it, so if building for a newer silicon rev or SPI is disabled, don't bother checking for the ksz. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-05-1011/+341
|\ | | | | | | | | | | | | Conflicts: drivers/usb/host/ehci-pci.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * powerpc/85xx: Enable eSDHC boot support on P2020 DSJerry Huang2011-04-04-1/+77
| | | | | | | | | | | | | | | | | | | | | | We implement our own mmc_get_env_addr since the environment variables are written to just after the u-boot image on SDCard, so we must read the MBR to get the start address and code length of the u-boot image, then calculate the address of the env. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add 36-bit address map support to P1022DSJiang Yutang2011-04-04-0/+3
| | | | | | | | | | Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDBPoonam Aggrwal2011-04-04-4/+8
| | | | | | | | | | | | | | | | Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Optimized DDR settings for 800MT/s on P1/P2 RDBPoonam Aggrwal2011-04-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Removed P1/P2 RDB RevB supportPoonam Aggrwal2011-04-04-22/+7
| | | | | | | | | | | | | | | | RevB boards never really made it outside of Freescale and have been replaced with RevC & RevD which had various board bug fixes. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Read board switch settings on p1_p2_rdbPriyanka Jain2011-04-04-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width. On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI] switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdbPriyanka Jain2011-04-04-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl: obsolete NXID v0 EEPROMs, automatically upgrade them to NXID v1Timur Tabi2011-04-04-10/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NXID EEPROM format comes in two versions, v0 and v1. The only difference is in the number of MAC addresses that can be stored. NXID v0 supports eight addresses, and NXID v1 supports 23. Rather than allow a board to choose which version to support, NXID v0 is now considered deprecated. The EEPROM code is updated to support only NXID v1, but it can still read EEPROMs formatted with v0. In these cases, the EEPROM data is loaded and the CRC is verified, but the data is stored into a v1 data structure. If the EEPROM data is written back, it is written in v1 format. This allows existing v0-formatted EEPROMs to continue providing MAC addresses, but any changes to the data will force an upgrade to the v1 format, while retaining all data. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Update fixed DDR3 timing table for P4080DSYork Sun2011-04-04-8/+8
| | | | | | | | | | | | | | | | | | Most of time U-boot doesn't get an exact clock number. For example, clock 900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the table to align the desired clocks in the middle. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-542/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-144/+2
| | | | | | | | | | | | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Remove config.mk for nand linker scriptKumar Gala2011-04-04-121/+0
| | | | | | | | | | | | | | Move the include of mpc85xx/u-boot-nand.lds to utilize CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc: Move cpu specific lmb reserve to arch_lmb_reserveKumar Gala2011-04-04-93/+5
| | | | | | | | | | | | | | | | We've been utilizing board_lmb_reserve to reserve the boot page for MP systems. We can just move this into arch_lmb_reserve for 85xx & 86xx systems rather than duplicating in each board port. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add eSDHC support on P2020DSJerry Huang2011-04-04-0/+13
| | | | | | | | | | | | | | | | | | | | | | We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9 respectively). We enable EXT2, FAT, and parition support for both MMC & USB configs. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>Kumar Gala2011-04-04-6/+0
| | | | | | | | | | | | | | | | | | Remove declerations of fsl_ddr_set_memctl_regs in board files with and place it into a common header. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr initKumar Gala2011-04-04-35/+28
| | | | | | | | | | | | | | | | | | | | Rather than having #defines DATARATE_*_MHZ, lets just match what we do on the SPD code and convert the DDR frequency into MHZ and just compare with a constant. Based on patch from Poonam Aggrwal. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * p1022ds: allow for board-specific ngPIXIS functionsTimur Tabi2011-04-04-18/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC SOCs. Although programming the ngPIXIS is mostly standard on all boards that have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in "indirect" mode whenever the video display (DIU) is active. To support indirect mode, and to make it easier to support other quirks on future reference boards, the low-level ngPIXIS functions are all marked as weak, so that board-specific code can override any of them. We take advantage of this feature on the P1022DS, so that we can properly reset the board when the DIU is active. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | MIPS: Purple: Remove Purple supportDaniel Schwierzeck2011-04-02-1239/+0
|/ | | | | | | | The Purple SoC and eval board are not actively maintained since years. This patch removes the support completely as aggreed with Wolfgang Denk. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2011-03-27-4/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-03-27-164/+190
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| * SMDK6400: Fixup dram_init for relocation supportseedshope2011-03-27-1/+7
| | | | | | | | | | Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Fix the mutiple link errorseedshope2011-03-27-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | The first, the cpu_init.o have already been link for cmd_link_o_target atfer compile, But, The link script re-link the point file. So the link machine will generate multiple definition error information. The second, Since the first 4kB of nand boot featue code move to nand_spl, So It is not necessary to force the cpu_init.o in non-nand boot. Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * SMDK6400: Fix some label undefined in build errorseedshope2011-03-27-3/+24
| | | | | | | | | | | | | | | | | | | | Modify Makefile for cpu_init.c and Start.s use some label,this defined u-boot.lds of arch/arm/cpu/arm1176. But SMDK6400 use the link script board/samsung/smdk6400/u-boot-nand.lds. So add some label form u-boot.lds to u-boot-nand.lds Signed-off-by: Zhong Hongbo <bocui107@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * rename _end to __bss_end__Po-Yu Chuang2011-03-27-160/+160
| | | | | | | | | | | | | | Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* | powerpc/85xx: Fix PCI memory map setup on P1_P2_RDBPrabhakar Kushwaha2011-03-24-2/+2
| | | | | | | | | | | | | | | | | | Update the PCIe address map to match standard FSL memory map. Additionally, fix the TLBs so the cover the PCIe address space properly so cards plugged in like an e1000 work correctly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/mpc8572ds: revise board specific timing for dual-rank DIMMsYork Sun2011-03-24-32/+78
|/ | | | | | | | Tested all possible values for clk_adjust and write_data_delay for dual rank UDIMM and RDIMM to revise the tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc52xx, digsy_mtc_rev5: Fix Linux crash, if no Flash in bank 2Heiko Schocher2011-03-21-0/+5
| | | | | | | | | | | | | | | | If no Flash is connected to cs1, Linux crashes, because reg entries are not correct adapted. Following fix is needed: - swap base addresses in CONFIG_SYS_FLASH_BANKS_LIST, as flash bank 1 is on chipselect 0 and flash bank 2 on chipselect 1 - call fdt_fixup_nor_flash_size() from ft_board_setup() Signed-off-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <hs@denx.de> cc: Werner Pfister <Pfister_Werner@intercontrol.de> cc: Detlev Zundel <dzu@denx.de>
* powerpc/corenet_ds: revise platform dependent parametersYork Sun2011-03-05-4/+4
| | | | | | | | This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* corenet_ds: pick the middle value for all tested timing parametersYork Sun2011-03-05-40/+18
| | | | | | | | | | | For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent. The best values should be picked up from the middle of all working combinations. This patch updates the table with confirmed values tested on Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s, 900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s, 1200MT/s, 1000MT/s. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-10 05:48:01 +0000