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authorShaohui Xie <b21989@freescale.com>2011-03-16 10:10:32 +0800
committerKumar Gala <galak@kernel.crashing.org>2011-04-10 11:17:55 -0500
commit2a9fab82b74d59aa9150e905aa06a6bff32c5059 (patch)
tree7c10e2b21c9368186b5c576fe4864f32d605ac57 /board
parentf378017ffa53fbf8bf3530b25a589fba771a2ffb (diff)
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powerpc/85xx: Add PBL boot from SPI flash support on P4080DS
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/corenet_ds/tlb.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c
index 1ae0416..fe77e79 100644
--- a/board/freescale/corenet_ds/tlb.c
+++ b/board/freescale/corenet_ds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -51,9 +51,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,