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* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-10-12-38/+26
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
| * armv7: LS1021a: enable i-cache in start.SXiaoliang Yang2016-10-06-0/+12
| | | | | | | | | | | | | | | | | | | | Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First stage of u-boot can run faster after that. There is a description about skip lowlevel init in board/freescale/ls1021atwr/README. Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl_sec_mon: Update driver for Security MonitorSumit Garg2016-10-06-38/+14
| | | | | | | | | | | | | | | | | | | | | | Update the API's for transition of Security Monitor states. Instead of providing both initial and final states for transition, just provide final state for transition as Security Monitor driver will take care of it internally. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> [York Sun: Reformatted commit message slightly] Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-08-154/+436
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| * | arm: imx: add i.MX6ULL 14x14 EVK board supportPeng Fan2016-10-04-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6ULL EVK board support: Add device tree file, which is copied from NXP Linux. Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR. The uart iomux settings are still keeped in board file. Boot Log: U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800) CPU: Freescale i.MX6ULL rev1.0 at 396MHz CPU: Commercial temperature grade (0C to 95C) at 15C Reset cause: POR Model: Freescale i.MX6 ULL 14x14 EVK Board Board: MX6ULL 14x14 EVK DRAM: 512 MiB MMC: initialized IMX pinctrl driver FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1 is current device Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | mx6sabresd: Make SPL DDR configuration to match the DCD tableFabio Estevam2016-10-04-154/+197
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. This causes stability issues like the ones reported at 7dbda25ecd6d7c ("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also: http://lists.denx.de/pipermail/u-boot/2016-September/266355.html . As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Retrieved the DCD tables from: board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg and board/freescale/mx6sabresd/mx6qp.cfg (NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga) This method makes it easier for people converting from non-SPL to SPL code. Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* | spi: Move freescale-specific code into a private headerSimon Glass2016-10-06-18/+39
|/ | | | | | | | | | | | | | At present there are two SPI functions only used by freescale which are defined in the spi_flash.h header. One function name matches an existing generic SPL function. Move these into a private header to avoid confusion. Arcturus looks like it does not actually support SPI, so drop the SPI code from that board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* usb: fsl: Rename fdt_fixup_dr_usbSriram Dash2016-09-27-26/+26
| | | | | | | | The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-427/+2011
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun2016-09-26-3/+51
| | | | | | | | | | | | | | | | | | Instead of using multiple macros, a data structure is used to pass board-specific parameters to MMDC DDR driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-14-4/+1084
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046ardb: Add LS1046ARDB board supportMingkai Hu2016-09-14-0/+751
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-348/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-14-1/+6
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-14-1/+34
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-13/+0
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+24
| | | | | | | | | | | | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+28
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set individual device access permissionHou Zhiqiang2016-09-14-14/+20
| | | | | | | | | | | | | | | | Add this API to make the individual device is able to be set to the specified permission. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-14-32/+0
| | | | | | | | | | | | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: ls1043ardb: move sec_init to board_initSumit Garg2016-09-14-15/+17
| | | | | | | | | | | | | | | | | | | | sec_init() which was earlier called in misc_init_r() is now done in board_init() before PPA init as SEC block will be used during PPA image validation. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-10/+10
| | | | | | | | | | | | | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* | arch, board: squash lines for immediate returnMasahiro Yamada2016-09-23-3/+1
|/ | | | | | | | Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Angelo Dureghello <angelo@sysam.it>
* mx6ul_14x14_ev: Enable the CCGR clocks earlierFabio Estevam2016-09-06-2/+2
| | | | | | | | | | | To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init(). Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD"). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Tested-by: Eric Nelson <eric@nelint.com>
* mx6ul_14x14_evk: Adjust SPL DDR3 settingsFabio Estevam2016-09-06-7/+7
| | | | | | | | Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
* mx6ul_14x14_evk: Pass refsel and refr fields to avoid hangFabio Estevam2016-09-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk, we observe a hang when going into the lowest operational point of cpufreq. This hang issue does not happen on the NXP U-Boot version. After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting: DATA 4 0x021B0020 0x00000800 ,which means: REF_SEL = 0 --> Periodic refresh cycle: 64kHz REFR = 1 ---> Refresh Rate - 2 refreshes So adjust the MDREF initialization for mx6ul_evk accordingly to fix the kernel hang issue at low bus frequency. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
* mx6: ddr: Allow changing REFSEL and REFR fieldsFabio Estevam2016-09-06-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
* mx7dsabresd: Directly write to register LDOGCTLFabio Estevam2016-09-06-3/+1
| | | | | | | | | Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* mx7dsabresd: Directly write to register LDOGCTLFabio Estevam2016-09-06-3/+1
| | | | | | | | | Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* mx6ul_14x14_evk: don't use array for SD2 card detect padEric Nelson2016-09-06-14/+10
| | | | | | | | | Only a single pad is changed to change sdhc2_dat3 from an SDIO pin to and from GPIO4:5, so remove the array and use the imx_iomux_v3_setup_pad() routine. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* mx7dsabresd: Print secure/non-secure mode infoFabio Estevam2016-09-06-1/+8
| | | | | | | | | | | | mx7dsabresd has two targets: - mx7dsabresd_defconfig: boots in non-secure mode - mx7dsabresd_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* treewide: fix "followings" to "following"Masahiro Yamada2016-08-26-1/+1
| | | | | | Most of them are my mistakes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* board/freescale: Update MAINTAINERS filesYork Sun2016-08-02-9/+17
| | | | | | Update maintainers for secure boot targets. Signed-off-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-7/+5
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| * mx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfigFabio Estevam2016-07-28-0/+1
| | | | | | | | | | | | Add an entry for the mx7dsabresd_secure_defconfig target. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6ul_14x14_evk: Remove unused defineDiego Dorta2016-07-28-3/+0
| | | | | | | | | | | | | | Remove unused define constant. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6sxsabresd: Avoid hardcoded RAM sizeVanessa Maegima2016-07-12-1/+1
| | | | | | | | | | | | | | | | Instead of passing the total RAM size via PHYS_SDRAM_SIZE option, we should better use imx_ddr_size() function, which automatically determines the RAM size. Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
| * mx6sxsabreauto: Avoid hardcoded RAM sizeVanessa Maegima2016-07-12-1/+1
| | | | | | | | | | | | | | | | | | Instead of passing the total RAM size via PHYS_SDRAM_SIZE option, we should better use imx_ddr_size() function, which automatically determines the RAM size. Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6slevk: Avoid hardcoded RAM sizeVanessa Maegima2016-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | Instead of passing the total RAM size via PHYS_SDRAM_SIZE option, we should better use imx_ddr_size() function, which automatically determines the RAM size. Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx6qsabreauto: Avoid hardcoded RAM sizeVanessa Maegima2016-07-12-1/+1
| | | | | | | | | | | | | | | | | | Instead of passing the total RAM size via PHYS_SDRAM_SIZE option, we should better use imx_ddr_size() function, which automatically determines the RAM size. Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
* | armv8: ls1043aqds: add IFC fixup in case QSPI is enabledQianyu Gong2016-07-26-0/+10
| | | | | | | | | | | | | | | | | | QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is enabled, IFC would not be initialized correctly. So disable the IFC node for Linux. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-26-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: ls1043aqds: Update MAINTAINERSYork Sun2016-07-26-0/+1
| | | | | | | | | | | | Add ls1043aqds_lpuart_defconfig to file list. Signed-off-by: York Sun <york.sun@nxp.com>
* | armv8: ls2080aqds: Update MAINTAINERSYork Sun2016-07-26-0/+1
| | | | | | | | | | | | Add ls2080aqds_qspi_defconfig to file list. Signed-off-by: York Sun <york.sun@nxp.com>
* | arm: ls1021atwr: Add SD secure boot targetSumit Garg2016-07-26-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SD secure boot target for ls1021atwr. Implement board specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* | SECURE_BOOT: Enable chain of trust in SPL frameworkSumit Garg2016-07-26-1/+33
| | | | | | | | | | | | | | | | | | | | | | Override jump_to_image_no_args function to include validation of u-boot image using spl_validate_uboot before jumping to u-boot image. Also define macros in SPL framework to enable crypto operations. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8/ls1043ardb: Integrate FSL PPAHou Zhiqiang2016-07-19-1/+7
| | | | | | | | | | | | | | | | | | The PPA use PSCI to make secondary cores bootup. So when PPA was enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method between PSCI and spin-table. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | armv8: Move secure_ram variable out of generic global dataYork Sun2016-07-15-35/+40
|/ | | | | | | Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-30 04:37:17 +0000