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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2016-08-02 19:03:26 +0800
committerYork Sun <york.sun@nxp.com>2016-09-14 14:07:08 -0700
commit664b6520582fcea7e150f57258c7a63627837318 (patch)
tree12d0456f8dfe80a95eb52f1209d39c1c24f86f50 /board/freescale
parentc37fdbdbb0dd65cb4aa147c9cf9352901014be3b (diff)
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fsl: csu: add an API to set R/W permission to PCIe
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/common/ns_access.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index c3d7a5e..81c9211 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <fsl_csu.h>
#include <asm/arch/ns_access.h>
+#include <asm/arch/fsl_serdes.h>
void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
{
@@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void)
{
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
}
+
+void set_pcie_ns_access(int pcie, u16 val)
+{
+ switch (pcie) {
+#ifdef CONFIG_PCIE1
+ case PCIE1:
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
+ return;
+#endif
+#ifdef CONFIG_PCIE2
+ case PCIE2:
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
+ return;
+#endif
+#ifdef CONFIG_PCIE3
+ case PCIE3:
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
+ set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
+ return;
+#endif
+ default:
+ debug("The PCIE%d doesn't exist!\n", pcie);
+ return;
+ }
+}