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* MLK-13525-2 mx7ulp_evk: Add plugin boot supportYe Li2016-11-25-2/+229
| | | | | | | Add plugin boot support for EVK board. The DDR init codes are updated to v1.2 DDR script. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13509 mx7ulp_evk: Update DDR script to v1.2Ye Li2016-11-25-1/+4
| | | | | | | | | | | | | | | | | | | | DDR script is updated to v1.2 for EVK board to fix DQS gating issue and add pre-charge .That DQS sampling may have problem after we enabling the SDE_0/SDE_1 in MDCTL. Changes: -Issue a Precharge-All command prior to the MRW Reset command. setmem /32 0x40AB001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 -Based on V1.1, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: EVK_IMX7ULP1_LPDDR3_320MHz_1GB_32bit_V1.2.inc Test: Passed stress test on 1 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13508-2 mx6sllarm2: Update DDR script to v2.3Ye Li2016-11-24-9/+11
| | | | | | | | | | | | | | | | | | | DDR scripts are updated to fix DQS gating issue commonly for LPDDR2 and LPDDR3. That DQS sampling may have problem after enabling the SDE_0/SDE_1 in MDCTL. Changes: -Based on V2.2, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1 Test: Passed stress test on 1 LPDDR2 ARM2 board and 1 LPDDR3 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13508-1 mx6sllevk: Update DDR script to v2.2Ye Li2016-11-24-4/+5
| | | | | | | | | | | | | | | | | | DDR script is updated to v2.2 to fix potential DQS gating issue. That DQS sampling may have problem after enabling the SDE_0/SDE_1 in MDCTL. Changes: -Based on V2.1.1, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1 Test: Passed stress test on two boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-19 imx: mx7ulp_evk: Add EVK boards support codesYe Li2016-11-22-0/+435
| | | | | | | | | | | | | | Add basic support for i.MX7ULP EVK board. I2C, SD/eMMC, UART, QSPI and USB are added. Use target mx7ulp_evk_config to select the configuration. Use mx7ulp_evk_emmc_config for eMMC boot. Use mx7ulp_evk_m4boot_config for binding and booting m4 image in single boot mode. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13499 imx6sll: add epdc splash screen supportRobby Cai2016-11-21-0/+442
| | | | | | | add splash screen feature for epdc. it's tested on imx6sll arm2 board and evk board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-13440-3 mx6sll_arm2: Update USDHC2 parameter for using 1.8V I/OYe Li2016-11-08-6/+2
| | | | | | | | Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC. Also remove the explicit USDCH2 vendorspec register settings in board codes, since the driver will take charge of it. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13440-2 mx6sllevk: Update USDHC2 parameter for using 1.8V I/OYe Li2016-11-08-6/+2
| | | | | | | | Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC. Also remove the explicit USDCH2 vendorspec register settings in board codes, since the driver will take charge of it. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13405-4 mx6sll-arm2: change the eMMC reset pad to 1.8vHaibo Chen2016-11-04-2/+6
| | | | | | | | | | eMMC is connected fixed to 1.8v, so need to set the LVE of pad sd2_rst. Also need to set the VSELECT to change all the eMMC pad (cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and SD3 voltage switch. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* MLK-13405-3 mx6sll-evk: change the eMMC reset pad to 1.8vHaibo Chen2016-11-04-2/+6
| | | | | | | | | | eMMC is connected fixed to 1.8v, so need to set the LVE of pad sd2_rst. Also need to set the VSELECT to change all the eMMC pad (cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and SD3 voltage switch. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* MLK-13407: mx6qarm2: mt128x64mx3 2: add init pre charge all commandAdrian Alonso2016-10-31-3/+10
| | | | | | | | | | | | | - Adjust ZQ delay for MMDC clock frequency at 400MHz - Precharge all commands per JEDEC The memory controller may optionally issue a Precharge-All command prior to the MRW Reset command, this is strongly recommended to ensure a robust DRAM initialization DDR Calibration script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/a72e010a1fd8c7fe0fda7bdc4d058c478e94c3da Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13289 imx: mx6sxscm: generic mx6sxscm board supportJuan Gutierrez2016-10-26-0/+1321
| | | | | | | | | | | | | | Provide the generic support for i.MX6SX SCM boards i.MX6SX SCM board file with the generic configuration, LPDDR2 memory calibration and build support is provided. - LPDDR2 memory configuration files for 1GB and 512MB. - plugin support for the above configurations. - driver support for: uart, qspi, i2c, usb, mmc. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13255 imx: mx6dqscm: generic mx6dqscm board supportJuan Gutierrez2016-10-21-0/+2537
| | | | | | | | | | | | | Provide the generic support for i.MX6DQ SCM boards - LPDDR2 memory configuration files for 1GB, 2GB and 512MB. - plugin support for the above configurations. - fix and interleave memory mode (selected by CONFIG option) - driver support for: uart, spi, i2c, usb, sata and fec. - Android support Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13373 mx6sll: update ddr script to 2.1.1Peng Fan2016-10-21-4/+4
| | | | | | | | | | | | | | | | Update ddr script to 2.1.1 Script: http://compass.freescale.net/livelink/livelink/235732623/EVK_IMX6SLL_LPDDR3_400MHz_512MB_32bit_V2.1.1.txt?func=doc.Fetch&nodeid=235732623 Version 2.1.1: -Update [MMDC_MPRDDLCTL] and [MMDC_MPWRDLCTL] based on calibration results -setmem /32 0x021B0848 = 0x3F393B3C // [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration Register -setmem /32 0x021B0850 = 0x262C3826 // [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration Register Tested on two boards. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13352 imx: mx6sll: support mx6sllevk boardPeng Fan2016-10-19-0/+796
| | | | | | | | | | Add mx6sll evk board support. USB/LCDIF/I2C/SD/EMMC/WDOG supported. The ddr script is from mx6sll lpddr3 arm2 board. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13336 mx6sll_arm2: Update LPDDR2 script to v2.1Ye Li2016-10-13-3/+10
| | | | | | | | | | | | | | | | | | | | Changes: Version 2.1 -Issue a Precharge-All command prior to the MRW Reset command. setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results setmem /32 0x021B0848 = 0x3A383C40 // [MMDC_MPRDDLCTL] setmem /32 0x021B0850 = 0x242C3020 // [MMDC_MPWRDLCTL] File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Passed overnight memtester on one i.MX6SLL LPDDR2 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13331 mx6sll_arm2: Output WDOG_B signal to reset PMICYe Li2016-10-12-0/+8
| | | | | | | Since the LPDDR2/3 does not have reset pin, to keep safe reset, we need to use WDOG_B to reset PMIC. Add pinmux and relevant settings. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13330 mx6sll_arm2: Update LPDDR3 script to v2.2Ye Li2016-10-12-7/+14
| | | | | | | | | | | | | | | | | | | | | | | Changes from v1.2 to v2.2: Version 2.2 -Issue a Precharge-All command prior to the MRW Reset command. -setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 -setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 Version 2.1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results -setmem /32 0x021B0848 = 0x3C3A3C3C // [MMDC_MPRDDLCTL] -setmem /32 0x021B0850 = 0x24293625 // [MMDC_MPWRDLCTL] Version 1.2.1 -Fix a typo. setmem /32 0x020E052C = 0x00000030 -Fix a typo. setmem /32 0x021B0800 = 0xA1390003 File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Overnight memtester passed on two i.MX6SLL LPDDR3 ARM2 boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13307-15 imx: mx6sll: add mx6sll arm2 supportPeng Fan2016-10-11-0/+1068
| | | | | | | | | | | Add mx6sll lpddr3/lpddr2 arm2 support. LCDIF/SPI/USB/PMIC supported. LPDDR3 DDR version: 1.2 LPDDR2 DDR version: initial version. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13131: mx6qarm2: add fastboot and recovery supportAdrian Alonso2016-09-13-0/+33
| | | | | | Add fastboot and recovery mode support for mx6qarm Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividersAdrian Alonso2016-09-07-1/+1
| | | | | | | | Adjust ahb/axi clock root podf dividers to be divided by 1 to allow ahb/axi clock root to be 24Mhz when sourced from osc_clk. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13141 mx6qpsabresd: Do not touch VGEN3 and VGEN5Robin Gong2016-08-30-12/+14
| | | | | | | | VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board, so software didn't need to change their voltage output anymore. Otherwise, VGEN3 will be wrongly updated from 1.8v to 2.8v. Signed-off-by: Robin Gong <yibin.gong@nxp.com>
* MLK-13115 imx: mx6ullevk: Update LPDDR2 script for i.MX6ULL 9x9 EVKYe Li2016-08-23-4/+4
| | | | | | | | | | | | | | | | | | Update the LPDDR2 script to 1.2 rev with delay line settings changed. File: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspx Changes: Update Delay Line Settings based on the delay line calibration results of more boards. MMDC_MPRDDLCTL = 0x40403439 MMDC_MPWRDLCTL = 0X4040342D Test: One 9x9 EVK board pass stress memtester. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13070 imx: mx6ullevk: Add 9x9 EVK supportYe Li2016-08-12-21/+17
| | | | | | | | | | | | | | | | Add two build configs for i.MX6ULL 9X9 EVK. And update lpddr2 script for the board to version 1.0. DDR script: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.0.inc Changes: Initial version Test: Passed memtester overnight test on 1 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12929 imx6ull: support splash screen for epdcRobby Cai2016-07-29-0/+221
| | | | | | | add splash screen feature for epdc. it's tested on imx6ull arm2 board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATAYe Li2016-07-29-4/+14
| | | | | | | | | | | | | | We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before this changing, SATA read/write can't work after it. And we have to re-init SATA. The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing. This patch is an work around that moves the ENET clock setting (enable_fec_anatop_clock) from ethernet init to board_init which is prior than SATA initialization. So there is no PLL6 change after SATA init. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12988 imx: mx6ull Add board support for i.MX6ULL EVKYe Li2016-07-19-0/+1695
| | | | | | | | | | | | | | | | | | | | | Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok to work. The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when it is needed. The DDR3 script is using version 1.2: File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc Test: 3 boards passed memtester. Build target: mx6ull_14x14_evk_defconfig Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12889 mx6ullarm2: Update DDR script to version 2.2Ye Li2016-06-08-2/+2
| | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.2.inc Changes: Change MMDC_MDMISC.WALAT to 1 setmem /32 0x021B0018 = 0x00211740 Test: Passed memtester on two mx6ull ddr3 arm2 boards Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output settingYe Li2016-06-06-1/+1
| | | | | | | | | LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3 is actually 1.2V. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
* MLK-12815: mx6ul_14x14_evk: add new NAND config for i.MX6UL 14x14 EVK boardHan Xu2016-05-23-0/+2
| | | | | | | | add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when NAND enabled due to pin conflict. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)
* MLK-12800 imx: mx7dsabresd: support revCPeng Fan2016-05-16-4/+13
| | | | | | Add revC board support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLLYe Li2016-05-16-0/+10
| | | | | | | | | | | | In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flowAnson Huang2016-05-09-1/+13
| | | | | | | | | | | | On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. For LPSR mode, ddr resume flow is same as retention mode, just adjust it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-2 imx: remove IOMUXC GPR setting for i.mx7d retention modeAnson Huang2016-05-09-3/+3
| | | | | | | | i.MX7D TO1.2 removes the DDR PADs retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-1 imx: adjust i.mx7d standby voltage settingAnson Huang2016-05-09-14/+14
| | | | | | | i.MX7D VDD_ARM/SOC standby voltage should be 0.95V, adding 25mV margin, so set it to 0.975V; Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12629-2: i.MX6QP: update pluginPeng Fan2016-05-04-0/+12
| | | | | | For i.MX6QP, the QoS settings is different from others. Align with DCD. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12735 mx6qpsabresd: Update DDR script to version 1.14Ye Li2016-04-29-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)
* MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2Anson Huang2016-04-29-59/+59
| | | | | | | | i.MX7D TO1.2 uses same DDR script as TO1.0, TO1.1 uses dedicated DDR script. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 527d57e02b05eb0166dcaa1929e46dd2357a8720)
* MLK-12694 mx6ullarm2: Remove the CD detection of SD2Ye Li2016-04-22-3/+1
| | | | | | | | | | Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause SD2 access problem even the card is inserted. Hard code the CD result to 1 to assume the card is always on. The SD driver will return other errors if the card does not exist. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 47efe2fda62297ab1da8594828cd7bd928ecbda7)
* MLK-12687 mx6ullarm2: Clean up macro usage for pins conflict devicesYe Li2016-04-21-8/+8
| | | | | | | | | | | | | | | 1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which conflicts with QSPIA and NAND, that we have to disable them at same time. 2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which conflicts with SD2 and NAND, that we have to disable them at same time. 3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK 4. Enable QSPI support for default SD boot case. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)
* MLK-12690 imx: mx6ull: fix build error for pluginPeng Fan2016-04-21-1/+1
| | | | | | | | | Fix build error for Plugin "Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor" Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 95860f1213c038ef2e5900d1874ff5398ac0be2a)
* MLK-12677 mx6ullarm2: Update DDR script to version 2.1Ye Li2016-04-20-5/+6
| | | | | | | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc Changes: Change ZQ_OFFSET to the default value:00 setmem /32 0x021B0890 = 0x00400000 Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11 setmem /32 0x020E0288 = 0x000C0030 Change duty cycle fine tune cell for SDCLK and SDQS setmem /32 0x021B08C0 = 0x00944009 Test: One mx6ull ARM2 board passed memtest. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8128b2f3b419a1d15a0489a91e56a4ac82eaf0c4)
* MLK-12616-11 imx: mx6ull: add mx6ull arm2 board supportPeng Fan2016-04-13-0/+1120
| | | | | | | | | | | | | Support mx6ull ddr3 arm2 board. DDR script version 1.1. Passed memtester on 3 boards. Take mx6ul 14x14 ddr3 arm2 as reference. Note: LCD/NAND/ECSPI not tested, need hardware rework. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 584050b98cf070bb608b652e89659ff20c47efba)
* MLK-12563: imx: mx6ul evk: fix LCD_nPWREN settingPeng Fan2016-03-25-1/+1
| | | | | | | Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3. If LCD_nPWREN is high, output is 2.4V which is not correct. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12551: imx6ul evk: fix 74LV OE usagePeng Fan2016-03-25-7/+1
| | | | | | | | | | | Fix 74LV OE gpio index. pinmux is correct, but gpio index is wrong, so gpio output will not have effect, since we use wrong GPIO5_IO18, but not correct GPIO5_IO8. And at the end of the initialization of 74lv init, should keep OE voltage level at LOW, but not high. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12483-5 mx6ul: Enable module fuse check EVK board and DDR3 ARM2 boardYe Li2016-03-25-1/+58
| | | | | | | Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for module fuse check. And modify board level codes for SD, FEC and EIM. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12442: imx: mx6qarm2: lpddr2 set dram 2 channel fixed modeAdrian Alonso2016-03-25-2/+12
| | | | | | | | | | | | | Setup MMDC in two channel fixed mode Initialize dram banks for two channel fixed mode DRAM bank = 0x00000000 -> start = 0x10000000 -> size = 0x20000000 DRAM bank = 0x00000001 -> start = 0x80000000 -> size = 0x20000000 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-12371-2: imx: mx7dsabresd: fix POR reset failed after DDR enter retentionRobin Gong2016-03-25-0/+9
| | | | | | | Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR retention mode before uboot boot, so add this in DCD and plugin code. Signed-off-by: Robin Gong <yibin.gong@nxp.com> (cherry picked from commit 62248ef80dabbd7601ff4e2969368d7bf54896d9)
* MLK-12555-3 mx7dsabresd: Remove the SRS setting for wdogYe Li2016-03-25-6/+0
| | | | | | | Since the WDOG driver has updated to clear SRS at software assertion of WDOG. We don't need this in board level. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12555-2 mx6ulevk: Enable the Watchdog WDOG_B signal outputYe Li2016-03-25-0/+2
| | | | | | | | When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com>
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