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* mpc8260: remove MPC8266ADS board supportMasahiro Yamada2015-01-05-1101/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rune Torgersen <runet@innovsys.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-01-02-0/+41
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| * imx:mx6slevk add spi nor boot supportPeng Fan2014-12-31-0/+1
| | | | | | | | | | | | | | Add spi nor boot support for mx6slevk board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * imx:mx6sxsabresd add qspi supportPeng Fan2014-12-31-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the pad setting and enable qspi clock to support qspi flashes access. Add QSPI related macro in configuration header file. Note: mx6sxsabresd Revb board, 32M flash is used, but in header file, CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT initialization qspi_set_lut function uses 32BIT addr, however CONFIG_SPI_FLASH_BAR and 24BIT addr should be used to access bigger than 16MB size flash, and BRRD/BRWR should also be supported. Future patches will fix this. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | mx6slevk: Remove get_board_rev()Fabio Estevam2014-12-30-5/+0
| | | | | | | | | | | | | | | | | | | | get_board_rev() just returns the cpu revision, which does not make it really useful for distinguishing between revisions of the board. Let's get rid of get_board_rev() as it is not being used with its correct meaning. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx51evk: Fix MX51EVK_USB_CLK_EN_B definitionFabio Estevam2014-12-19-1/+1
| | | | | | | | | | | | As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx:mx6qarm2 add board level support for usbPeng Fan2014-12-19-0/+42
| | | | | | | | | | | | Add pinmux settings and implement board_ehci_hcd_init Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | imx:mx6sabresd add board level support for usbPeng Fan2014-12-19-0/+68
|/ | | | | | Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* mpc85xx/t104xrdb: convert deep sleep to generic board interfaceTang Yuantian2014-12-15-29/+33
| | | | | | | | A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-1/+98
|\ | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * imx:mx6sxsabresd add board level support for usbPeng Fan2014-11-14-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6sxsabresd board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to make host port work in HOST mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
| * imx:mx6slevk add board level support for usbPeng Fan2014-11-14-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-16/+756
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| * | ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-0/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1021aqds: add hwconfig setting to do pin muxYao Yuan2014-12-11-3/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale LS1021AQDS share some pins, so Add the hwconfig option that allows the user to choose which the function he wants. The main pin mux IP is: eSDHC, SAI, IIC2, RGMII, CAN, SAI. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang2014-12-11-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add SD boot support for LS1021ATWR boardAlison Wang2014-12-11-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-1/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macroAlison Wang2014-12-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Through adding CONFIG_QIXIS_I2C_ACCESS macro, QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used for both i2c and ifc access to QIXIS FPGA. This is more convenient for coding. Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1021aqds: set the default I2C channel before DDR initChenhui Zhao2014-12-11-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | When resuming from deep sleep, the I2C channel may not be in the default channel. So, switch to the default channel before accessing DDR SPD. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-2/+2
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| * | arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)Stefan Roese2014-12-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As checkpatch complaines about these camel-case defines, lets change them to only use upper-case characters. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | powerpc/hydra: fix judging condition of RGMII selectionMinghuan Lian2014-12-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BRDCFG1_EMI1_SEL_MASK has been changed to 0x78, which contains selection bits and connected status bit. So the Corresponding mux value of RGMII is changed to BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/hydra: Update MDIO mux fixupsChunhe Lan2014-12-05-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new device trees use a more generic interface for supporting muxing mdio buses. The mux property is thus specified in "reg", rather than "fsl,hydra-mdio-muxval". In order to support using old device trees, we keep the old fixup in there. Linux will therefore see the both properties, but will ignore fsl,hydra-mdio-muxval. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | board/t1024qds: add retimer support on t1024qdsShengzhou Liu2014-12-05-0/+57
| | | | | | | | | | | | | | | | | | | | | Initialize retimer for XFI on t1024qds. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | t1024qds: increase IO drive strengthShengzhou Liu2014-12-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | board/t1024qds: update pin multiplexingShengzhou Liu2014-12-05-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add multiplexing support among SPI flash, TDM riser card and SDXC. it routes SPI pins to SPI flash by default. Route SPI pins to SD slot if "adaptor=sdxc" is set in hwconfig. Route SPI pins to TDM riser card and do fixup for dts if "pin_mux=tdm" is set in hwconfig. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/t1024rdb: Add T1024 RDB board supportShengzhou Liu2014-12-05-0/+1169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/t1024qds: Add T1024 QDS board supportShengzhou Liu2014-12-05-0/+1736
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1024QDS is a high-performance computing evaluation, development and test platform for T1024 QorIQ Power Architecture processor. T1024QDS board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Three 1G/2.5Gbps SGMII ports - Four 1Gbps QSGMII ports - one 10Gbps XFI or 10Base-KR interface - SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora - PCIe: Three PCI Express controllers with five PCIe slots. - IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - Video: DIU supports video up to 1280x1024x32 bpp. - Chrontel CH7201 for HDMI connection. - TI DS90C387R for direct LCD connection. - Raw (not encoded) video connector for testing or other encoders. - QUICC Engine block - 32-bit RISC controller for flexible support of the communications peripherals - Serial DMA channel for receive and transmit on all serial channels - Two universal communication controllers, supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - eSPI: Three SPI flash devices. - SATA: one SATA 2.O. - USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC. - I2C: Four I2C controllers. - UART: Two UART on board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/t2080: updating rcw for silicon v1.1Shengzhou Liu2014-12-05-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0, and also update core frequency to 1.8GHz for v1.1. We reserve the support for T2080 v1.0 and enable v1.1 by default. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfigSuresh Gupta2014-12-05-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp respectively in hwconfig. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/b4860qds: add workaround for XFIShaohui Xie2014-12-05-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XFI does not work stable on current board, it's due to heat sink issue, to make it work stable the board needs additional heat sink, enable two XFI lanes only. Right now we do not have such an erratum for the issue, so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it. The workaround will only be used in XFI protocols and only if the hwconfig indicates that XFI is prefered. A new VSC3308 config function is used instead of re-use the original function, to avoid making the function complex and ugly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | B4860QDS: Enable SFP or AMC on basis of hwconfig stringSuresh Gupta2014-12-05-8/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes2 lanes EFGH either go to SFP or AMC riser card slot2. By default AMC will be configured even if no hwconfig is specified. To enable XFI via SFP use the below hwconfig: fsl_b4860_serdes2:sfp_amc=sfp Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@ffeescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/b4860qds: dtb fixup for xfiShaohui Xie2014-12-05-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Since xfi has no phy, we delete the property "phy-handle" and use a "fixed-link" property for a xfi port. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/b4860qds: add xfi supportShaohui Xie2014-12-05-7/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need following changes to make xfi work on B4: 1. set cross-point switch VSC3308 to use sfp config when running xfi; 2. add 10G interface check for xfi; 3. set phy address for xfi so the 10G ports can be registered by mdio; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | B4860: Add alternate LC VCO serdes protocols support in board fileShaveta Leekha2014-12-05-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support of newly added LC VCO SerDes protocols for configuration of IDT and VSC crossbar Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | B4860QDS: SGMII related updatesShaveta Leekha2014-12-05-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Enable SGMII support for 0x8d Serdes 2 protocol. - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol. - Updated debug statement - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1) - Rename onboard PHY address defines for more readability - Add these new Defines in B4860QDS.h file Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/b4860: Enable law creation of MAPLEShaveta Leekha2014-12-05-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | B4860, B4440, B4420 and B4220 have MAPLE, so enable law creation for them only. Remove static LAW creation for MAPLE. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/t208xqds: VID supportYing Zhang2014-12-05-0/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | board/t104xrdb: Conditional workaround of errata A-008044Prabhakar Kushwaha2014-12-05-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Workaround of Errata A-008044 was implemented without errata number and it is enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0. So put errata number and make it conditional. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | powerpc/mpc85xx:Put errata number for T104x NAND boot issuePrabhakar Kushwaha2014-12-05-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When device is configured to load RCW from NAND flash IFC_A[16:31] are driven low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using IFC_A[16:31] lines are not accessible. Workaround is already in-place. Put the errata number to adhere errata handling framework. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | mpc85xx/t208xqds: Adjust DDR timing parametersYork Sun2014-12-05-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust timing for dual-rank UDIMM, verified on M3CQ-8GHS3C0E for speed of 1066, 1333, 1600, 1866MT/s. The 1866 timing is copied to 2133 timing in case such DIMM comes available. Also update single-rank 1866 timing. Enable interactive debugging as well. Signed-off-by: York Sun <yorksun@freescale.com> CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-26-9/+36
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| * | | arm: ls102xa: Select ge2_clk125 for eTSEC clock muxingAlison Wang2014-11-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1 as other functionality except RGMII. The workaround is to select ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR boardAlison Wang2014-11-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board. As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC. As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Remove bit reversing for SCFG registersAlison Wang2014-11-24-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode. Address: 157_0000h base + 200h offset = 157_0200h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W/R SCFGREV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31 SCFGREV SCFG Bit Reverse Control Filed 32'h 0000_0000 - No bit reverse is applied 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31 This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi write 0x570200, 0xffffffff .end So other SCFG register could be written in big-endian mode in u-boot or kernel directly. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-05 08:58:17 +0000