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* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-3/+1
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-2/+2
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-16-3/+3
| | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* powerpc/mpc8xxx: Merge entries in DDR speed tableYork Sun2011-10-09-101/+102
| | | | | | | | | | | | | | | It is not necessary to keep multiple entries for the same setting in DDR speed tables. Merge them for smaller tables. Also restructure the tables for smaller size. Cleanup some typedefs. Enforce strict checking for speed table. If DIMM is running at higher than known speed, try to use the highest speed setting. If rank is unknown, it has to panic. Removed ODT overriding for P2020DS as it is not necessary. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc85xx: Display a warning for unsupported DDR data ratesYork Sun2011-07-11-4/+4
| | | | | | | | If DDR initialziation uses a speed table and the speed is not matched, print a warning message instead of silently ignoring. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-23/+0
| | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-5/+0
| | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8572ds: revise board specific timing for dual-rank DIMMsYork Sun2011-03-24-32/+78
| | | | | | | | Tested all possible values for clk_adjust and write_data_delay for dual rank UDIMM and RDIMM to revise the tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add ddr interleaving suppport for MPC8572DS boardHaiying Wang2008-10-18-28/+94
| | | | | | | | | | | | | | | | * Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-1/+4
| | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-0/+81
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>