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* NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUSTTom Rini2017-01-24-0/+2
| | | | | | | | | Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8: LS1043A: Enable LS1043A default PSCI supportmacro.wave.z@gmail.com2016-12-15-0/+9
| | | | | | | | | | A most basic PSCI implementation with only one psci_version is added for LS1043A, this can verify the generic PSCI framework, and more platform specific implementation will be added later. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/board/ddr: optimize board-specific cpo for erratum A-009942Shengzhou Liu2016-12-15-0/+3
| | | | | | | | | | Optimize board-specific cpo for erratum A-009942 on b4860qds, ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb, t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb, t4qds, t4rdb boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+4
| | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-14-5/+0
| | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls1043ardb: move sec_init to board_initSumit Garg2016-09-14-15/+17
| | | | | | | | | | sec_init() which was earlier called in misc_init_r() is now done in board_init() before PPA init as SEC block will be used during PPA image validation. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board/freescale: Update MAINTAINERS filesYork Sun2016-08-02-1/+1
| | | | | | Update maintainers for secure boot targets. Signed-off-by: York Sun <york.sun@nxp.com>
* ARMv8/ls1043ardb: Integrate FSL PPAHou Zhiqiang2016-07-19-1/+7
| | | | | | | | | The PPA use PSCI to make secondary cores bootup. So when PPA was enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method between PSCI and spin-table. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Move secure_ram variable out of generic global dataYork Sun2016-07-15-7/+8
| | | | | | | Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Organize SoC overview at common locationPrabhakar Kushwaha2016-06-03-35/+2
| | | | | | | | | | SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board/freescale: Update ddr clk_adjustShengzhou Liu2016-06-03-3/+3
| | | | | | | | | This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1043ardb: invert irq pin polarity for AQR105 PHYShaohui Xie2016-05-18-0/+4
| | | | | | | | | To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1043ardb: fix types of variablesQianyu Gong2016-05-18-3/+3
| | | | | | | Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls1043a: remove redundant code in board filesQianyu Gong2016-05-18-5/+0
| | | | | | | | | gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043ardb: fix the limitation of using 'cpld reset'Qianyu Gong2016-05-18-2/+25
| | | | | | | | | | The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-8/+5
| | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* board: ls1043ardb: Modify pin-muxing code for USB and QE-HDLCZhao Qiang2016-02-24-10/+43
| | | | | | | | | QE-HDLC and USB multi-use the pins, modify the pin-muxing code for them, when set "hwconfig=qe-hdlc" in uboot, assign the pins to QE-HDLC, if not, assgin it to USB Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls1043rdb: Move USB muxing config to config_board_muxZhao Qiang2016-02-24-15/+15
| | | | | | | | Pin-muxing code should be in config_board_mux, move USB muxing config to config_board_mux. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls1043ardb: Add micro QE support for ls1043ardbZhao Qiang2016-02-24-0/+8
| | | | | Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043ardb/rcw: change core frequency to 1600MHzMingkai Hu2015-12-17-4/+4
| | | | | | | Change RCW for SD boot and NAND boot. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-1/+22
| | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-15-0/+15
| | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-1/+18
| | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: add USB supportGong Qianyu2015-11-30-0/+16
| | | | | | | Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls1043ardb: Add missing config entries to MAINTAINERSFabio Estevam2015-11-10-0/+2
| | | | | | | | | ls1043ardb_nand_defconfig and ls1043ardb_sdcard_defconfig are missing in the MAINTAINERS file, so add them for completeness. Reported-by: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* armv8/ls1043ardb: Add sd boot supportGong Qianyu2015-10-29-0/+33
| | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-0/+1
| | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-0/+82
| | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-29-0/+42
| | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-29-0/+642
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
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