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author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-05-04 10:20:22 +0800 |
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committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:06:57 -0700 |
commit | e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 (patch) | |
tree | fe6ee40fd32a3abfe8f52b3cf797f5bc3172248b /board/freescale/ls1043ardb | |
parent | d8e5163ad81a2810c66a9a98e5111769378f5f5f (diff) | |
download | u-boot-imx-e04f9d0c2f5dec275eb550317c6bad2d8bbfb209.zip u-boot-imx-e04f9d0c2f5dec275eb550317c6bad2d8bbfb209.tar.gz u-boot-imx-e04f9d0c2f5dec275eb550317c6bad2d8bbfb209.tar.bz2 |
board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/ls1043ardb')
-rw-r--r-- | board/freescale/ls1043ardb/ddr.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index 8ca166b..a77ddf3 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,}, + {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, #endif {} }; |