| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
| |
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
|
|
|
|
| |
Patch by Stefan Roese, 29 May 2006
|
| |
|
|
|
|
|
|
|
|
| |
- Changed GPIO setup to enable another address line in order to
address 64M of FLASH.
- Added function sdram_tr1_set to auto calculate the tr1 value for
the DDR.
Patch by Steven Blakeslee, 12 Dec 2005
|
| |
|
|
|
|
| |
Patch by Stefan Roese, 27 Nov 2005
|
|
|
|
|
|
|
|
|
|
|
| |
On PPC44x platforms, the startup message generated in "cpu.c" only
comprised the ppc type and revision but not additional informations
like speed etc. Those speed infos where printed in the board specific
code. This new implementation now prints all CPU infos in the common
cpu specific code. No board specific code is needed anymore and
therefore removed from all current 44x implementations.
Patch by Stefan Roese, 27 Nov 2005
|
|
|
|
| |
Patch by Stefan Roese, 05 Nov 2005
|
|
|
|
| |
Patch by Stefan Roese, 03 Nov 2005
|
|
|
|
|
|
|
| |
The multiplexed signals Ext IRQ0...3 have to be configured as IRQ,
because they default to GPIOx (440EP/GR).
Patch by Stefan Roese, 28 Oct 2005
|
|
|
|
| |
Patch by Stefan Roese, 3 Oct 2005
|
|
|
|
|
| |
boards (baudrate, environment...). Flash driver fixed.
Patch by Stefan Roese, 15 Sep 2005
|
|
|
|
|
| |
Pointed out by Gerhard Jaeger, 31 Aug 2005;
cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
|
|
|
|
|
| |
now handling all 4xx cpu's.
Patch by Stefan Roese, 16 Aug 2005
|
| |
|
|
Patch by Steven Blakeslee, 27 Jul 2005
|