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* omap4460: add ES1.1 identificationAneesh V2011-12-06-1/+12
| | | | Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4: emif: fix error in driverAneesh V2011-12-06-2/+2
| | | | | | | | | | There was a typo in the EMIF driver. It went un-noticed because it affected only when automatic detection is enabled and even then half the memory was configured and identified properly. Reported-by: Rockefeller <rockefeller.lin@innocomm.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* omap: remove I2C from SPLAneesh V2011-12-06-1/+0
| | | | | | | Due to some recent changes I2C is no longer required in SPL. Remove the i2c_init() call to save some space Signed-off-by: Aneesh V <aneesh@ti.com>
* omap4460: fix TPS initializationAneesh V2011-12-06-8/+0
| | | | | | | | | | | TPS power IC is controlled using a GPIO (gpio_wk7). This GPIO should be maintained at logic 1 always. As such an internal pull-up on this pin will do the job, driving the GPIO outuput is not needed. This will avoid the need of using GPIO library in SPL and also may save some power. Signed-off-by: Aneesh V <aneesh@ti.com>
* start.S: remove omap3 specific code from start.SAneesh V2011-12-06-23/+9
| | | | | | | Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Tom Rini <trini@ti.com>
* armv7: setup vectorAneesh V2011-12-06-0/+17
| | | | | | | | The vector is not correctly setup in armv7 except for OMAP3. Correcting this. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: include armv7/cpu.c in SPL buildAneesh V2011-12-06-2/+2
| | | | | | | | | This allows SPL to have default implementation of save_boot_params(), useful for SoCs that do not intend to override this default implementation Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: disable L2 cache in cleanup_before_linux()Aneesh V2011-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | We were not disabling external caches before jumping to kernel. We were flushing all caches including external caches and disabling caches globally in CP15 System Control register. Apparently this is not enough. The bootstrap loader in Linux kernel that does decompression enables data-caches again, flush them after use and disable them before jumping to kernel proper. However, it's not aware of the external caches. Since we have left external cache enabled, external cache will get used once caches are enabled globally, but it's not flushed because decompressor is not aware of external caches. When it jumps to kernel with caches disabled globally, we have stale data in the external cache and a coherency problem. This was breaking the boot for OMAP4 with latest mainline kernel. The solution is to disable external caches in cleanup_before_linux(). With this fix kernel is booting again. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
* arm, arm926ejs: Fix clear bss loop for zero length bssChristian Riesch2011-12-06-3/+5
| | | | | | | | This patch fixes the clear bss loop for bss sections that have zero length, i.e., where __bss_start == __bss_end__. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* PXA: Rename pxa_dram_init to pxa2xx_dram_initMarek Vasut2011-12-06-3/+3
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Export cpu_is_ and pxa_dram_init functionsMarek Vasut2011-12-06-0/+29
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Replace timer driverMarek Vasut2011-12-06-52/+35
| | | | | | This new timer driver shall conform to new Timer API. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Add cpuinfo display for PXA2xxMarek Vasut2011-12-06-0/+134
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Separate PXA2xx CPU initMarek Vasut2011-12-06-73/+31
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]XMarek Vasut2011-12-06-44/+44
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Re-add the Dcache locking as RAM for pxa250Marek Vasut2011-12-06-2/+116
| | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefan Herbrechtsmeier <sherbrec@cit-ec.uni-bielefeld.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* PXA: Rework start.S to be closer to other ARMsMarek Vasut2011-12-06-247/+153
| | | | | | | | | | The start.S on PXA was very obscure. This reworks it back to be close to arm1136 start.S and others. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> V2: Don't compile in relocation support if building SPL
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingWolfgang Denk2011-12-05-6/+1
|\ | | | | | | | | | | | | | | | | | | * 'agust@denx.de' of git://git.denx.de/u-boot-staging: Makefile: add tools/mkenvimage to target 'clean' mv_common.c: get rid of 'defined but not used' warning m68k: fix ambiguous bit testing sparc: fix unknown escape sequence warnings sparc: fix unused variable warnings sf: fix erase debug output
| * m68k: fix ambiguous bit testingMike Frysinger2011-12-05-1/+1
| | | | | | | | | | | | | | | | | | | | Building for some m68k boards results in the warning: cpu_init.c: In function 'cpu_init_f': cpu_init.c:287: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * sparc: fix unused variable warningsMike Frysinger2011-12-05-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the build warnings: board.c: In function 'board_init_f': board.c:179:8: warning: unused variable 'e' board.c:178:6: warning: unused variable 'i' board.c:173:13: warning: unused variable 'cmdtp' bootm.c: In function 'do_bootm_linux': bootm.c:101:28: warning: unused variable 'kernend' bootm.c:101:15: warning: unused variable 'initrd_addr' bootm.c:100:26: warning: unused variable 'checksum' bootm.c:100:21: warning: unused variable 'len' bootm.c:100:15: warning: unused variable 'data' Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | sh: Add support Renesas SH7724Nobuhiro Iwamatsu2011-12-02-0/+236
| | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | sh: avoid multiple definition errors with cache funcsMike Frysinger2011-12-02-21/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Recent builds for SH4 boards fail with a lot of errors like: cmd_mem.o: In function 'dcache_invalid_range': include/asm/cache.h:25: multiple definition of 'dcache_invalid_range' include/asm/cache.h:25: first defined here This is due to the funcs being defined in the header, but not static or inline or extern. So move them to the sh4-specific cache.c file. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | sh: Add ashrsi3 libgcc functionPhil Edworthy2011-12-02-0/+186
| | | | | | | | | | | | | | | | | | | | | | The ashrsi3 function is used by some commands that aren't in SH2A default configs (e.g. JFFS2). The ashrsi3.S file has been copied from Linux. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | sh: only add -mno-fdpic if the compiler supports itMike Frysinger2011-12-02-1/+2
|/ | | | | | | | | Not all SuperH toolchains support -mno-fdpic. Chances are good that if the flag doesn't work, it isn't defaulting to the FDPIC ABI, so the flag isn't needed. So only add it if it is actually supported. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warningWolfgang Denk2011-12-02-3/+0
| | | | | | | | | | | Fix: cpu.c: In function 'checkcpu': cpu.c:51:7: warning: variable 'ver' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Kumar Gala <galak@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-12-01-24/+158
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: mpc85xx: support for Freescale COM Express P2020 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warning mpc85xx: support board-specific reset function powerpc/85xx: verify the localbus device tree address before booting the OS mpc8xxx: update module_type values from JEDEC DDR3 SPD Specification powerpc/p3060qds: Add board related support for P3060QDS platform powerpc/85xx: clean up and document the QE/FMAN microcode macros powerpc/85xx: always implement the work-around for Erratum SATA_A001 powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.h powerpc/85xx: Add workaround for erratum A-003474 powerpc/85xx: fixup flexcan device tree clock-frequency powerpc/85xx: Add workaround for erratum CPU-A003999
| * mpc85xx: support for Freescale COM Express P2020Ira W. Snyder2011-11-29-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warningKumar Gala2011-11-29-2/+1
| | | | | | | | | | | | | | | | | | Fix: interactive.c: In function 'fsl_ddr_interactive': interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: support board-specific reset functionIra W. Snyder2011-11-29-1/+16
| | | | | | | | | | | | | | | | | | This is useful for boards which cannot be reset in the usual way for the 85xx CPU. An example is a board which can only be reset by a hardware watchdog. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: verify the localbus device tree address before booting the OSTimur Tabi2011-11-29-9/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The localbus controller node in the device tree is typically a root node, even though the controller is part of CCSR. If we were to put the lbc node under the SOC node, then the 'ranges' property in the lbc node would translate through the 'ranges' property of the parent SOC node, and we don't want that. Since the lbc is a separate node, it's possible for the 'reg' property to be wrong. This happened with the original version of p1022ds.dts, which used a 32-bit value in the 'reg' address, instead of a 36-bit address. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8xxx: update module_type values from JEDEC DDR3 SPD SpecificationIra W. Snyder2011-11-29-0/+7
| | | | | | | | | | | | | | | | | | | | Newer JEDEC DDR3 SPD Specifications define several additional values for the DDR3 module_type field which were undefined when this code was written. Update the code to handle the newer module types. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: clean up and document the QE/FMAN microcode macrosTimur Tabi2011-11-29-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several macros are used to identify and locate the microcode binary image that U-boot needs to upload to the QE or Fman. Both the QE and the Fman use the QE Firmware binary format to package their respective microcode data, which is why the same macros are used for both. A given SOC will only have a QE or an Fman, so this is safe. Unfortunately, the current macro definition and usage has inconsistencies. For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address of NAND. There's no way to know by looking at a variable how it's supposed to be used. In the future, the code which uploads QE firmware and Fman firmware will be merged. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: always implement the work-around for Erratum SATA_A001Timur Tabi2011-11-29-4/+33
| | | | | | | | | | | | | | | | | | | | On the P1022/P1013, the work-around for erratum SATA_A001 was implemented only if U-Boot initializes SATA, but SATA is not initialized by default. So move the work-around to the CPU initialization function, so that it's always executed on the SOCs that need it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.hTimur Tabi2011-11-29-0/+6
| | | | | | | | | | | | | | | | | | | | | | Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA controller, so it should be defined in config_mpc85xx.h instead of the various board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013, P1022, P2041, P3041, P5010, and P5020. It was already defined for the P1010 and P1014. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add workaround for erratum A-003474York Sun2011-11-29-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-003474: Internal DDR calibration circuit is not supported Impact: Experience shows no significant benefit to device operation with auto-calibration enabled versus it disabled. To ensure consistent timing results, Freescale recommends this feature be disabled in future customer products. There should be no impact to parts that are already operating in the field. Workaround: Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following: 1. Write a value of 0x0000_0015 to the register at offset CCSRBAR + DDR OFFSET + 0xf30 2. Write a value of 0x2400_0000 to the register at offset CCSRBAR + DDR OFFSET + 0xf54 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: fixup flexcan device tree clock-frequencyJia Hongtao2011-11-29-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the fixup matchable with dts and kernel. Update the compatible from "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq" property to "clock-frequency". We also change flexcan frequency from CCB-clock to CCB-clock/2 according to P1010 spec. We now keep the old interfaces to make previous kernel work. They should be removed in the future. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add workaround for erratum CPU-A003999Kumar Gala2011-11-29-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | x86: Wrap small helper functions from libgcc to avoid an ABI mismatchGabe Black2011-11-29-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When gcc compiles some 64 bit operations on a 32 bit machine, it generates calls to small functions instead of instructions which do the job directly. Those functions are defined in libgcc and transparently provide whatever functionality was necessary. Unfortunately, u-boot can be built with a non-standard ABI when libgcc isn't. More specifically, u-boot uses -mregparm. When the u-boot and libgcc are linked together, very confusing bugs can crop up, for instance seemingly normal integer division or modulus getting the wrong answer or even raising a spurious divide by zero exception. This change borrows (steals) a technique and some code from coreboot which solves this problem by creating wrappers which translate the calling convention when calling the functions in libgcc. Unfortunately that means that these instructions which had already been turned into functions have even more overhead, but more importantly it makes them work properly. To find all of the functions that needed wrapping, u-boot was compiled without linking in libgcc. All the symbols the linker complained were undefined were presumed to be the symbols that are needed from libgcc. These were a subset of the symbols covered by the coreboot code, so it was used unmodified. To prevent symbols which are provided by libgcc but not currently wrapped (or even known about) from being silently linked against by code generated by libgcc, a new copy of libgcc is created where all the symbols are prefixed with __normal_. Without being purposefully wrapped, these symbols will cause linker errors instead of silently introducing very subtle, confusing bugs. Another approach would be to whitelist symbols from libgcc and strip out all the others. The problem with this approach is that it requires the white listed symbols to be specified three times, once for objcopy, once so the linker inserts the wrapped, and once to generate the wrapper itself, while this implementation needs it to be listed only twice. There isn't much tangible difference in what each approach produces, so this one was preferred. Signed-off-by: Gabe Black <gabeblack@chromium.org>
* | x86: Import the glibc memset implementationGabe Black2011-11-29-1/+89
| | | | | | | | | | | | | | The new implementation is about twice as fast as the old. This is from glibc-2.14, sysdeps/i386/memset.c. Signed-off-by: Gabe Black <gabeblack@chromium.org>
* | x86: Fix a few recently added bugsGabe Black2011-11-29-1/+6
| | | | | | | | | | Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Don't relocate symbols which point to things that aren't relocatedGabe Black2011-11-29-11/+8
| | | | | | | | | | | | | | | | This change adds an upper bound for symbols which are fixed up after u-boot is relocated into RAM. This way portions that are left at their original location can be referred to without having to manually fix up any pointers. Signed-off-by: Gabe Black <gabeblack@chromium.org>
* | x86: Fix how the location of the realmode and bios blobs are calculatedGabe Black2011-11-29-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two blobs embedded into the u-boot image which are linked to run at an address which is different from where they actually end up in the ROM, one called "realmode" and one called "bios". There are realmode_setup and bios_setup functions which prepare those blobs by copying them into the location they're supposed to run from, among other things. During u-boot relocation from ROM to RAM, the text and a few data segments are copied over. The realmode and bios sections are not copied, and so the only place they can be read from is their original location in the ROM. Looking specifically at the bios blob, there are symbols defined in the linker script called __bios_start and __bios_size which are defined to be the start and size of the blob in the ROM. In the bios_setup function, there seem to be two mistakes happening. First, the offset from ROM to RAM is being added to __bios_start which implies that this code expects to use the copy moved to RAM. No such copy is made, so that's wrong. More subtly, when u-boot relocates itself, it goes through all of the relocations stored in .rel.dyn and fixes them up. This has the effect of transforming the __bios_start reference in bios_setup so that it refers to the version in RAM (if one existed) instead of the one in ROM. To correct for that, the offset actually needs to be subtracted out again to translate the address back into the ROM. The net effect is that for both blobs, a + needs to be changed to a -. Signed-off-by: Gabe Black <gabeblack@chromium.org>
* | x86: Misc cleanupsGraeme Russ2011-11-29-2/+3
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Misc PCI touchupsGraeme Russ2011-11-29-7/+9
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Ensure IDT and GDT remain 16-byte aligned post relocationGraeme Russ2011-11-29-6/+13
| | | | | | | | | | | | Some CPUs have strict alignment requirements for these tables Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Provide more configuration granularityGraeme Russ2011-11-29-51/+56
| | | | | | | | | | | | Planned future ports requires more granularity for some options Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Add multiboot headerGraeme Russ2011-11-29-0/+20
| | | | | | | | | | | | | | | | | | By adding a multiboot header, U-Boot can be loaded by GRUB2. Using GRUB2 to bootstrap U-Boot is useful for using an existing BIOS to get an initial U-Boot port up and running before implementing the low-level reset vector code, SDRAM init, etc. and overwriting the BIOS Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | sc520: Create arch asm-offsetsGraeme Russ2011-11-29-47/+49
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Punt cold- and warm-boot flagsGraeme Russ2011-11-29-7/+0
| | | | | | | | | | | | | | Nobody uses them anyway Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | cosmetic: checkpatch cleanup of arch/x86/lib/*.cGraeme Russ2011-11-29-432/+516
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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