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| * | | armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-48/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver: net: fsl-mc: Add DPAA2 commands to manage MCPrabhakar Kushwaha2015-11-30-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management complex Firmware, DPL and DPC are depolyed during u-boot boot sequence. Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop and apply DPL from u-boot command prompt. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8: lsch3: Fix lane protocol parsing logicPrabhakar Kushwaha2015-11-30-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation only consider SGMIIs for dpmac initialization. XFI serdes protocols also uses dpmac. Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls1021a: Ensure Generic Timer disabled before jumping into the OSAlison Wang2015-11-30-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addresses a problem mentioned recently on this mailing list: [1]. In that posting a LS1021 based system was locking up at about 5 minutes after boot,but the problem was mysteriously related to the toolchain used for building u-boot.Debugging the problem reveals a stuck interrupt 29 on the GIC. It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value.This causes the timer compare to fire 344 seconds after u-boot configures it.Depending on how fast u-boot gets the kernel booted,this amounts to about 5-minutes of Linux uptime before locking up. Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. To fix the above issue, the generic physical timer is disabled before jumping to the OS. [1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html Signed-off-by: Chris Kilgour <techie@whiterocker.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bitAlison Wang2015-11-30-2/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addresses a problem mentioned recently on this mailing list: [1]. In that posting a LS1021 based system was locking up at about 5 minutes after boot, but the problem was mysteriously related to the toolchain used for building u-boot. Debugging the problem reveals a stuck interrupt 29 on the GIC. It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value. This causes the timer compare to fire 344 seconds after u-boot configures it. Depending on how fast u-boot gets the kernel booted, this amounts to about 5-minutes of Linux uptime before locking up. Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. At any rate this patch makes the manipulation explicitly 64-bit which alleviates the issue. [1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html Signed-off-by: Chris Kilgour <techie@whiterocker.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-11-30-0/+62
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| * | | arm: socfpga: dts: Adding drvsel and smplsel to dtsChin Liang See2015-11-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding new node drvsel and smplsel for SDMMC Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
| * | | arm: socfpga: Repair SoCrates boardMarek Vasut2015-11-30-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
| * | | ARM: socfpga: rename the cyclone5 and arria5 base address fileDinh Nguyen2015-11-30-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adding support for the Arria10 platform, we're going to name the file base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h to be base_addr_ac5.h for the Arria5 and Cyclone5 platform. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | | ARM: socfpga: arria10: add base address map for Arria10Dinh Nguyen2015-11-30-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | | arm: socfpga: reset: FIX address of tstscratch registerPhilipp Rosenberger2015-11-30-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cyclone V Hard Processor System Technical Reference Manual in the chapter about the Reset Manager Module Address Map stats that the offset of the tstscratch register ist 0x54 not 0x24. Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02 page 3-17 Reset Manager Module Address Map Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
* | | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2015-11-30-24/+1
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| * | | PPC4xx: Create "liebherr" vendor directoryWolfgang Denk2015-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation of some new Liebherr boards to be added soon, a new "liebherr" vendor directory gets created, and the "lwmon5" board directory is moved into this new vendor directory. cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Remove remnants from ocotea, taishan, ebony and taihuStefan Roese2015-11-30-23/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | The removal of some PPC4xx boards did not catch all references to these boards. This patch now removes all remnants still left. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-11-30-2/+2
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| * | | arm: s5pc1xx: move SoC to mach-s5pc1xxMinkyu Kang2015-11-30-2/+2
| |/ / | | | | | | | | | | | | | | | move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | arm: kirkwood: add ZyXEL NSA310S deviceGerald Kerma2015-11-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add ZyXEL NSA310S 1-Bay Media Server The ZyXEL NSA310S device is a Kirkwood based NAS: - SoC: Marvell 88F6702 1000Mhz - SDRAM memory: 256MB DDR2 400Mhz - Gigabit ethernet: PHY Marvell 88E1318 - Flash memory: 128MB - 1 Power button - 1 Power LED (blue) - 4 Status LED (green) - 1 Copy/Sync button - 1 Reset button - 1 SATA II port - 2 USB 2.0 ports (front and back) - Smart fan Signed-off-by: Gerald Kerma <dreagle@doukki.net> Signed-off-by: Tony Dinh <mibodhi@gmail.com> Signed-off-by: Luka Perkov <luka.perkov@sartura.hr>
* | | arm: mvebu: Configure ARP timeout and retry countStefan Roese2015-11-29-0/+2
|/ / | | | | | | | | | | | | | | | | | | As some MVEBU platforms using the MVNETA driver seem to miss the first ARP packet, lets reduce the timeout and increase the retry count. This increases the speed for communication establishment. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
* | am33xx: Remove serial_init in s_init for QSPI/NOR XIP bootVignesh R2015-11-23-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | serial_init() reads global_data, since global_data is not yet initialized, this can cause unwanted behaviour leading to QSPI XIP boot hang. Also, since serial_init() is anyways called later from boar_init_f(), it does not make sense to do the same in s_init(). Tested on AM437x IDK EVM with QSPI XIP boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-11-22-3/+1800
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| * | sunxi: Add support for the Lamobo R1 boardJelle de Jong2015-11-22-0/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lamobo-r1 board, sometimes called the BPI-R1 but not labelled as such on the PCB, is meant as a A20 based router board. As such the board comes with a built-in switch chip giving it 5 gigabit ethernet ports, and it has a large empty area on the pcb with mounting holes which will fit a 2.5 inch harddisk. To complete its networking features it has a Realtek RTL8192CU for WiFi 802.11 b/g/n. The dts file is identical to the one submitted upstream. Signed-off-by: Jelle de Jong <jelledejong@powercraft.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add H3 dts[i] filesHans de Goede2015-11-22-0/+825
| | | | | | | | | | | | | | | | | | | | | | | | These files are based on the current latest upstream kernel work. The bus_gates bindings may still change, but for u-boot that does not matter as we do not (yet) use any clock info from devicetree for sunxi u-boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3Siarhei Siamashka2015-11-22-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz on Allwinner H3 and using PLL6 as the clock source (PLL6/3). This can be verified by reading the value of the AHB1_APB1_CFG_REG register via /dev/mem. It always reads as 0x3180 regardless of the current cpufreq operating point. So this configuration should be safe for use in U-Boot too. PLL6 also needs to be configured before it is used as the clock source, according to the "CCU / Programming Guidelines" section of the Allwinner manual. The current low AHB1 clock speed is limiting the USB transfer speed when booting via FEL. This patch can increase the FEL USB transfer speed from ~510 KB/s to ~950 KB/s. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add H3 DRAM initialization supportJens Kuske2015-11-22-0/+660
| | | | | | | | | | | | | | | | | | | | | | | | Based on existing A23/A33 code and the original H3 boot0. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add basic H3 supportJens Kuske2015-11-22-0/+7
| |/ | | | | | | | | | | | | | | Add initial sun8i H3 support, only uart + mmc are supported for now. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | nios2: 10m50: change to ns16550 uartThomas Chou2015-11-21-1/+1
| | | | | | | | | | | | | | | | | | Change to ns16550 uart for 10m50 devboard based on a new Altera release. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ns16550: move CONFIG_SYS_NS16550 to KconfigThomas Chou2015-11-21-1/+0
| | | | | | | | | | | | Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* | ns16550: unify serial_tegraThomas Chou2015-11-21-0/+14
| | | | | | | | | | | | | | | | Unify serial_tegra, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ns16550: unify serial_rockchipThomas Chou2015-11-21-3/+5
| | | | | | | | | | | | | | | | | | Unify serial_rockchip, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* | ns16550: unify serial_ppcThomas Chou2015-11-21-0/+8
| | | | | | | | | | | | | | | | | | Unify serial_ppc, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add TODO comment] Signed-off-by: Tom Rini <trini@konsulko.com>
* | ns16550: unify serial_x86Thomas Chou2015-11-20-1/+1
|/ | | | | | | | | Unify serial_x86, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: test: usb: sandbox: Add keyboard tests for sandboxSimon Glass2015-11-19-0/+5
| | | | | | | Add a test that verifies that USB keyboards work correctly on sandbox. This verifies some additional parts of the USB stack. Signed-off-by: Simon Glass <sjg@chromium.org>
* usb: sandbox: Add a USB emulation driverSimon Glass2015-11-19-0/+2
| | | | | | | | | Add a simple USB keyboard driver for sandbox. It provides a function to 'load' it with input data, which it will then stream through to the normal U-Boot input subsystem. When the input data is exhausted, the keyboard stops providing data. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: test: usb: Add tests for the 'usb tree' commandSimon Glass2015-11-19-1/+13
| | | | | | | Add tests that this command produces the right output, even when a rescan results in a device disappearing from the bus. Signed-off-by: Simon Glass <sjg@chromium.org>
* test: Record and silence console in testsSimon Glass2015-11-19-0/+9
| | | | | | | | | When running sandbox tests, silence the console to avoid unwanted output. Also, record the console in case tests want to check it. The -v option can be used to enable stdout during tests. Signed-off-by: Simon Glass <sjg@chromium.org>
* Move console definitions into a new console.h fileSimon Glass2015-11-19-0/+6
| | | | | | | | The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Add a way to skip time delaysSimon Glass2015-11-19-1/+37
| | | | | | | | Some tests are slow due to delays which are unnecessary on sandbox. The worst offender is USB where we lose two seconds. Add a way to disable time delays. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Convert to use driver model keyboardBin Meng2015-11-19-0/+2
| | | | | | | Convert to use driver model keyboard on QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Convert to use driver model keyboardBin Meng2015-11-19-0/+1
| | | | | | | Convert to use driver model keyboard on Intel Crown Bay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add an i8042 device for boards that have itSimon Glass2015-11-19-0/+17
| | | | | | | | | | | | Some boards have an i8042 device. Enable the driver for all x86 boards, and add a device tree node for those which may have this keyboard. Also adjust the configuration so that i8042 is always separate from the VGA, and rename the stdin driver accordingly. With this commit the keyboard will not work, but it is fixed in the next commit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* sandbox: add a sandbox timer and basic testThomas Chou2015-11-19-0/+4
| | | | | | | | Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: cros_ec: Convert cros_ec keyboard driver to driver modelSimon Glass2015-11-19-0/+4
| | | | | | | | Adjust the cros_ec keyboard driver to support driver model. Make this the default for all Exynos boards so that those that use a keyboard will build correctly with this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: tegra: Convert keyboard driver to driver modelSimon Glass2015-11-19-0/+1
| | | | | | | | Adjust the tegra keyboard driver to support driver model, using the new uclass. Make this the default for all Tegra boards so that those that use a keyboard will build correctly with this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-11-19-0/+3
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| * ARM: am43xx: Enable QUAD read and EDMA support for ti_qspiVignesh R2015-11-17-0/+3
| | | | | | | | | | | | | | | | | | Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-11-19-3/+35
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| * | zynqmp: mp: Add support for booting R5 from any addressMichal Simek2015-11-19-3/+35
| | | | | | | | | | | | | | | | | | | | | Put jump trampoline to TCM at 0 and setup R5 reset address to 0. Jump trampoline ensures that jump to the right location. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | microblaze: Fix C99/gnu99 compatiblity for inline functionsNathan Rossi2015-11-19-43/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'extern inline' is not portable across various C standards. To ensure compatiblity with various standards/compilers change the functions to static inline. This is a portable construct and serves as a comparable definition to 'extern inline' from the gnu90 standard. Additionally remove the function prototypes as they are not required due to the functions being declared static and functions are correctly ordered based on dependence. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Tom Rini <trini@konsulko.com> Acked-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | microblaze: Fix style issues in header filesNathan Rossi2015-11-19-34/+34
|/ / | | | | | | | | | | | | | | | | | | Fix various style issues in MicroBlaze header files. Specifically fixing style voilations including '__inline__', 'foo * bar' and 'void foo ('. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | spl: mmc: add support for BOOT_DEVICE_MMC2Nikita Kiryanov2015-11-18-9/+1
| | | | | | | | | | | | | | | | | | | | | | Currently the mmc device that SPL looks at is always mmc0, regardless of the BOOT_DEVICE_MMCx value. This forces some boards to implement hacks in order to boot from other mmc devices. Make SPL take into account the correct mmc device. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-10-20 23:38:49 +0000