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| author | Marek Vasut <marex@denx.de> | 2015-11-23 17:06:27 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-11-30 13:30:19 +0100 |
| commit | 856b30dae54a9fa76a7457b6c891b3efd9a8a397 (patch) | |
| tree | db4398d8d5499aa62fa09d3124653a7e730fe05f /arch | |
| parent | 871c24bc501b035604123e5f6754b0b457678edb (diff) | |
| download | u-boot-imx-856b30dae54a9fa76a7457b6c891b3efd9a8a397.zip u-boot-imx-856b30dae54a9fa76a7457b6c891b3efd9a8a397.tar.gz u-boot-imx-856b30dae54a9fa76a7457b6c891b3efd9a8a397.tar.bz2 | |
arm: socfpga: Repair SoCrates board
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_socrates.dts | 5 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 7 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 6782691..05b935d 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -19,6 +19,10 @@ device_type = "memory"; reg = <0x0 0x40000000>; /* 1GB */ }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { @@ -37,6 +41,7 @@ &mmc0 { status = "okay"; + u-boot,dm-pre-reloc; }; &qspi { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a413ea4..e4cc468 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -22,6 +22,10 @@ config TARGET_SOCFPGA_DENX_MCVEVK bool "DENX MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_EBV_SOCRATES + bool "EBV SoCrates (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -38,11 +42,13 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -55,5 +61,6 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES endif |