summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
...
* MLK-14390-2 mx6sllarm2: Add DTS files for ARM2 boardYe Li2017-04-05-0/+862
| | | | | | | Copy the DTS files from kernel for LPDDR2/3 ARM2 board for preparing enabling the OF_CONTROL. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14390-1 mx6sllarm2: Add mx6sll LPDDR2/3 ARM2 board codesYe Li2017-04-05-0/+8
| | | | | | | Move the mx6sll lpddr2/3 arm2 board codes and defconfigs from v2016.03 as the base for converting to use DTB OF_CONTROL. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14380-2 mx6ullarm2: Add DTS files for ARM2 boardYe Li2017-04-05-0/+1159
| | | | | | | | | Copy the DTS files from kernel for DDR3 ARM2 board for preparing enabling the OF_CONTROL. Modify the QSPI n25q256a flash node's compatible to "spi-flash" for using DM SPI driver. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13602-1 mx6: Add i.MX6ULL fused modules checking supportYe Li2017-04-05-1/+44
| | | | | | | | Add the modules disable fuses mapping with FDT nodes and devices name. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit d033825f034467fa9c9aeff6fcf95a146c802cf1)
* MLK-12929 imx6ull: support splash screen for epdcRobby Cai2017-04-05-0/+56
| | | | | | | | add splash screen feature for epdc. it's tested on imx6ull arm2 board. Signed-off-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit bcdbe240bb2a97d38ba30dd244a51ece87662b06)
* MLK-14380-1 mx6ullarm2: Add mx6ull DDR3 ARM2 board codesYe Li2017-04-05-0/+8
| | | | | | | Move the mx6ull ddr3 arm2 board codes and defconfigs from v2016.03 as the base for converting to use DTB OF_CONTROL. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14382-2 mx6ularm2: Add DTS files for ARM2 boardsYe Li2017-04-05-1/+1606
| | | | | | | | | Copy the DTS files from kernel for DDR3 ARM2 board and LPDDR2 ARM2 board preparing for enabling OF_CONTROL. Modify the QSPI n25q256a flash node's compatible to "spi-flash" for using DM SPI driver. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14382-1 mx6ularm2: Add DDR3 and LPDDR2 ARM2 board codesYe Li2017-04-05-0/+16
| | | | | | | Move the mx6ul DDR3/LPDDR2 ARM2 boards codes from v2016.03 u-boot as the base for OF_CONTROL enabling. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-13 mx6ulevk: Add DTS filesYe Li2017-04-05-1055/+2938
| | | | | | | | | | Update i.MX6ul dtsi file and add mx6ul 14x14 and 9x9 evk DTS file to latest in kernel. To support DM QSPI driver, modify the DTS files with adding a spi0 alias for qspi node and changing the the n25q256a flash node's compatible to "spi-flash" Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-12 mx6sllevk: Update DTS filesYe Li2017-04-05-40/+51
| | | | | | Update i.MX6SLL dtsi file and mx6sll-evk DTS file to latest in kernel. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-10 mx6slevk: add DTS files and dt-binding header fileYe Li2017-04-05-0/+3037
| | | | | | | Update i.MX6SL dtsi file and dt-binding header files. Add the imx6sl-evk DTS file preparing for using DTB. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-8 mx6sxsabreauto: Update DTS file to latest in kernelYe Li2017-04-05-28/+793
| | | | | | | | Copy the imx6sx-sdb latest DTS file from imx_4.1.y kernel. To support DM QSPI driver, modify the n25q256a flash node's compatible to "spi-flash". Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-6 mx6sxsabresd: Update and add mx6sxsabresd DTS filesYe Li2017-04-05-109/+1593
| | | | | | | | | | | Update i.MX6SX dtsi file and relevant DTS header files. Add the imx6sx-sdb DTS files preparing for using DTB. To support DM QSPI driver 1. Modify the n25q256a flash node's compatible to "spi-flash". 2. Add spi0 and spi1 alias for qspi1 and qspi2. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-5 mx6qpsabreauto: Enable OF_CONTROL and DM driverYe Li2017-04-05-0/+184
| | | | | | | Update mx6qpsabreauto build configurations to use OF_CONTROL and DM driver. Also add the imx6qpsabreauto DTS file for using DTB. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-4 mx6dl/solosabreauto: Enable OF_CONTROL and DM driverYe Li2017-04-05-0/+121
| | | | | | | Update mx6dl/solosabreauto build configurations to use OF_CONTROL and DM driver. Also add the imx6dlsabreauto DTS file for using DTB. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-3 mx6qsabreauto: Enable OF_CONTROL and DM driverYe Li2017-04-05-0/+1284
| | | | | | | | | | | | | | Enable OF_CONTROL and DM driver on mx6qsabreauto. 1. Add the imx6qsabreauto relevant DTS file for using DTB. 2. Modify PMIC initialization codes to use DM PMIC driver. 3. Modify to use PCA953X DM driver 4. Remove NAND from default, since the default imx6q-sabreauto.dts disabled the nand. The pins are conflicted with UART3, while UART3 is enabled. 5. For NAND build configuration, remove the USB, since the imx6q-sabreauto-gpmi-weim.dts will have pin conflicts on steer logic. 6. GPIO requests added. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-2 mx6dlsabresd: Enable OF_CONTROL and DM driverYe Li2017-04-05-0/+153
| | | | | | | Enable OF_CONTROL and DM driver on mx6dlsabresd. And add the imx6dl sabresd DTS file for using DTB. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14326-1 mx6qpsabresd: Add DTS fileYe Li2017-04-05-0/+272
| | | | | | | Since we have enabled the i.MX6QP sabresd board with OF_CONTROL and DM driver. Add the imx6qp DTS file and imx6qp sabresd DTS file for build. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14375-3 mx6ullevk: Add 9x9 EVK board supportYe Li2017-04-05-0/+806
| | | | | | | | | | | | | | 1. Add build configs for i.MX6ULL 9X9 EVK. Enable DM I2C driver and DM PMIC driver for pfuze3000. Convert power init codes to use DM PMIC driver. 2. Add lpddr2 script IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc for the 9x9 board. Refer the commit 44a84b44a84cd1bdcc54d722987e5f109510891b 3. Add DTS file for 9x9 evk board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14375-2 mx6ullevk: Add DTS and build configuration for various boot devicesYe Li2017-04-05-0/+70
| | | | | | | To support boot from QSPI/NAND/eMMC, add relevant DTS files and build configurations. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14375-1 mx6ullevk: Update board codes to align with v2016.03Ye Li2017-04-05-12/+238
| | | | | | | | | | | | | | | | | | Update mx6ull evk to add features from v2016.03. 1. Add support for NAND flash. 2. Add support for QSPI DM driver. 3. Add USB DM driver support. 4. Add two FEC support by using DM FEC driver 5. Update environments for various boot devices support: SD/NAND/eMMC/QSPI 6. Add MFGtool environments. 7. Add board codes for 9x9 EVK board For the DTS file, some changes are needed for using QSPI DM driver 1. Add spi0 alias for qspi node. Which is used for bus number 0. 2. Modify the n25q256a@0 compatible property to "spi-flash". 3. Modify spi4 (gpio_spi) node to spi5 Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12416-9: mx6qp: define CONFIG_MX6QPPeng Fan2017-04-05-0/+3
| | | | | | | | Define CONFIG_MX6QP which will also set CONFIG_MX6Q, otherwise plugin code will use wrong ddr script. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 901d9eb01736ab54822678a197fe1aeb281a81b9)
* MLK-12531 mx6sxsabresd: Add CM4 fast boot up demoYe Li2017-04-05-0/+2
| | | | | | | | | | | | | | | | | | This is a demo that CM4 will boot up by u-boot without typing any command. It boots up at u-boot early init, try to minimize the time from power up to the CM4 running. Since CM4 runs on QSPI NOR XIP, we have to disable the QSPI driver in u-boot to avoid conflict. RDC for shared GPIO1 is added, but not enabled, because the kernel is not ready for shared GPIO1. Users can uncomment the CONFIG_IMX_RDC to enable it. Some legacy codes in mx6sxsabreauto are removed. We only need this work on mx6sxsabresd as a demo. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f66842f79d4e33ace45762466eed23a86d367642)
* MLK-12493-1 Add support for various boot deviceYe Li2017-04-05-0/+4
| | | | | | | | | | Add support for various boot devices like NAND, QSPINOR, SPINOR, eMMC, EIMNOR, SATA. Modify board level files to support the feature and add corresponding defconfig files Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 72c35e80b86f7f75a52db45959793882bb730793)
* MLK-12495 mx6: Add LDO bypass supportYe Li2017-04-05-2/+162
| | | | | | | | | | | | | | | | Port LDO bypass support from v2015 to support the features: 1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5b87d04dba66fa45375d59648838ef89f559f75d)
* MLK-14261-1 mx6solo: Rename the CONFIG_MX6SOLO to CONFIG_MX6SYe Li2017-04-05-1/+1
| | | | | | | | | | | | | Since there is already CONFIG_MX6S used for i.MX6 SOLO in u-boot codes, we don't need to add new CONFIG_MX6SOLO. Rename the existing CONFIG_MX6SOLO to CONFIG_MX6S. Additional, for CONFIG_MX6S, we should select CONFIG_MX6DL. The major difference for these two chips are core number and DDR controller. So all duallite relevant definitions can apply to solo. User can combine the two configs if any code only apply to solo or duallite. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2017-04-05-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82) (cherry picked from commit d85cd484e6825631aa1ab572e5e0539f2191d795) (cherry picked from commit 2b29c1873c2293abe1c4b361392521223b9c9ecf)
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2017-04-05-10/+52
| | | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit f735f8ac328aa49759f6db524f7c2ba32622f711)
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2017-04-05-2/+11
| | | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit afa2d78f2b799337eae3dc67c0ed702d5520eee6)
* MLK-12444-1 mfgtool: Add mfgtool supportYe Li2017-04-05-0/+7
| | | | | | | | | | | | | If boot from usb, reset environment to default value. Auto apply mfgtools setting and boot mfgtools kernel. Porting this from fsl uboot to uboot 2016. The 7dsabresd has already added the environment and usb boot related functions. No need to add them more. Only need to add NAND parts environment for mfgtools. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a352ed3c5184b95c4c9f7468f5fbb5f43de5e412)
* MLK-14259-3 mx6ulevk: Add support for NANDYe Li2017-04-05-0/+13
| | | | | | | Add NAND pinmux settings, clock setting and related configurations. Default not enabled, need hardware rework. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12767 imx6ull: fix runtime checking for i.MX6ULLPeng Fan2017-04-05-3/+3
| | | | | | | | Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 05922b0abf848949df778c19312cb1cf7fdfbe6a)
* MLK-12565 mx7: rdc: Change IS_ENABLED to remove build warningYe Li2017-04-05-2/+3
| | | | | | | | Change to use #ifdef not the IS_ENABLED, because we will get build warning when the CONFIG_IMX_RDC is not set. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a212eff242efb8dc171479cbaca34049d508f87b)
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2017-04-05-4/+4
| | | | | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63) (cherry picked from commit f7c5cf580fcc2c8ab95a8d835f5874d26216910f) (cherry picked from commit 1a90b60731cd60feba1ef7a11ede2613283bb4a8)
* MLK-12483-4 mx6: Modify drivers to disable fused modulesYe Li2017-04-05-9/+8
| | | | | | | | | | | Add the fuse checking in drivers, when the module is disabled in fuse, the driver will not work. Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C, USB-EHCI, GIS, LCDIF. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
* MLK-12483-3 mx6: Add a module fuse checkingYe Li2017-04-05-1/+401
| | | | | | | | | | | | | | | | Implement a functionality to read the soc fuses and check if any module is fused. For fused module, we have to disable it in u-boot dynamically, and change the its node in FDT to "disabled" status before starting the kernel. In this patch, we implement the ft_system_setup for FDT fixup. This function will be called during boot process or by "fdt systemsetup" command. To enable the module fuse checking, two configurations must be defined: CONFIG_MODULE_FUSE CONFIG_OF_SYSTEM_SETUP Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7236051526b73a5a25cc8330a79f5c08b7d70726)
* ENGR00315894-55 iMX6SX: add debug monitor supportYe.Li2017-04-05-0/+20
| | | | | | | | | | | | | | Debug monitor will print out last failed AXI access info when system reboot is caused by AXI access failure, only works when debug monitor is enabled. Enable this module on i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit df6ac8531d498021ed379c74fc1847bd2cec7179) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 4f4ecdbf6fe2673b8ad117df1a4974bdb7e6aa4a)
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2017-04-05-2/+31
| | | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71) (cherry picked from commit 3d25e2acd48f605678a98cf594a715809dea8286)
* MLK-10496: Check the PL310 version for applying errataNitin Garg2017-04-05-9/+18
| | | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
* MLK-10176-6 imx: mx7: Modify GPT timer driver for mx7Peng Fan2017-04-05-2/+8
| | | | | | | | | | | | | Modify the GPT common platform driver for mx7 which only use 24Mhz OSC as clock source. Note: at default, the mx7d will use system counter as timer. The GPT is disabled. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6e250796d6a07d84093eeae96e5a6e4c593cdb0b) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 708898fe547bd3d56f0abf7e40f1af91cf4271cf)
* ENGR00328312 i2c: imx: Optimize the i2c device recovery solutionFugang Duan2017-04-05-2/+26
| | | | | | | | | | | | | | | | | | | From i2c spec, if device pull down the SDA line that causes i2c bus dead, host can send out 9 clock to let device release SDA. But for some special device like pfuze100, it pull down SDA line and the solution cannot take effort. The patch just add NACK and STOP signal after 8 dummy clock, and pmic can release SDA line after the recovery. Test case catch 375 times of i2c hang, and all are recovered. Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit 53118db42d201d36ca9067b4bb0e2702399e100b) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b8dcb812401026cb2189b24a4f6058830151c85a) (cherry picked from commit c5a44a2a0b2218221cb12645b10f0b34ecc6f79b)
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2017-04-05-5/+0
| | | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640) (cherry picked from commit 850f27d137a083a141c99fe9828d596807937d38)
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2017-04-05-0/+10
| | | | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee) (cherry picked from commit f20a65847577ff40dc7e3739a0bb69926885c734)
* MLK-12557 mx6ul: Enable syscounter as default timerYe Li2017-04-05-3/+14
| | | | | | | | | Use syscounter for i.MX6UL platform as default timer, not use GPT. Add a CONFIG_GPT_TIMER for selecting GPT. Using CONFIG_SYSCOUNTER_TIMER for selecting system counter. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1c27c9ecf80b3cc63a7c9751ebfd11755f847b1d)
* ENGR00325255 pcie:enable pcie support on imx6sx sdYe Li2017-04-05-5/+35
| | | | | | | | | | | | | | | | | Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. (cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307) Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 81fd30250110d72992758f08b66c07306126892b)
* ENGR00319965 pcie: mask the imx6sl outRichard Zhu2017-04-05-15/+20
| | | | | | | | | | imx6sl doesn't have the pcie module, mask the pcie related codes from imx6sl. Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit acaff11da33f8f0cb1521d3c48e64e7ed9a87bec) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 48a4606ef575c72e16e31c167dce042fcb66191c)
* ENGR00319415 pcie: random link down issue after warm-rstRichard Zhu2017-04-05-0/+18
| | | | | | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 5cc825b12c6b86a22f1a6a0535b52cf3ee142e77) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 6193cf4e3384a59e29546d13a67657f7faeafc9e) (cherry picked from commit 7b4aabeddffabca46d7d6e7ef2611de468a6b4f7)
* MLK-11064 imx: mx6qp: Adjust AQos settings for peripheralsYe.Li2017-04-05-0/+3
| | | | | | | | | | | To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 11906c712a52e7a20caf71d7c5da4e951a59db29) (cherry picked from commit 5dcf073b8f2479a2adbb8d9fb03d9c9c70664e32)
* MLK-12534 mx6: shutdown vddpu and PCIE phy to save powerYe Li2017-04-05-0/+42
| | | | | | | | | | | | | | | | | | | Shutdown VDDPU and PCIE phy to save power. For PCIE, the i.MX6SL and i.MX6UL does not have this module, so don't need it. For VDDPU, the i.MX6UL does not have GPU, does not need it. And on i.MX6QP there is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Reference: commit: 6b0787b726e2ff32210d742d93ecd3f4bb2ae402 commit: 4bd0032c0eba50fa0caf43f50f735a3cfbe36a8d Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5c96ea91fe89c67991c929c9b39ffaa940d28391)
* MLK-12533 mx6sx: select OSC as uart's clk parentYe Li2017-04-05-0/+13
| | | | | | | | | | | As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Anson Huang <b20788@freescale.com> (cherry picked from commit b5e1b393192099e91c5cb75b69291c87eacb9f60) (cherry picked from commit 416dea861c2dd5a197bf2354069bba8415a20b12)
generated by cgit v1.1 at 2024-11-17 20:15:42 +0000