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| author | Nitin Garg <nitin.garg@freescale.com> | 2015-03-31 20:37:36 -0500 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:04:34 +0800 |
| commit | 071808ed7690fc7ac4069320e2b7a7988f596f4d (patch) | |
| tree | 9ad658c084a534b62b4f75d5a638e60295caa95c /arch | |
| parent | 8503bcf92a07b212a0f25b9650bd90aedf0b2039 (diff) | |
| download | u-boot-imx-071808ed7690fc7ac4069320e2b7a7988f596f4d.zip u-boot-imx-071808ed7690fc7ac4069320e2b7a7988f596f4d.tar.gz u-boot-imx-071808ed7690fc7ac4069320e2b7a7988f596f4d.tar.bz2 | |
MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369
Under very rare timing circumstances, transitioning into streaming
mode might create a data corruption. Present on Two or more processors
or 1 core with ACP, all revisions. This erratum can be worked round
by setting bit[22] of the undocumented Diagnostic Control Register to 1.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 70ad44e523680de67dd8b7a7505d7f27799980ee)
(cherry picked from commit f20a65847577ff40dc7e3739a0bb69926885c734)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/Kconfig | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 6 |
3 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0a05662..323ff0b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -85,6 +85,9 @@ config ARM_ERRATA_833069 config ARM_ERRATA_833471 bool +config ARM_ERRATA_845369 + bool + config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 401d916..bbd560f 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -7,6 +7,7 @@ config MX6 select ARM_ERRATA_751472 if !MX6UL select ARM_ERRATA_761320 if !MX6UL select ARM_ERRATA_794072 if !MX6UL + select ARM_ERRATA_845369 if !MX6UL config MX6D bool diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7eee54b..43aba71 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -9,6 +9,7 @@ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> * Copyright (c) 2003 Kshitij <kshitij@ti.com> * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> + * Copyright (C) 2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -186,6 +187,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 21 @ set bit #21 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_845369 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 22 @ set bit #22 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov r5, lr @ Store my Caller mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) |