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* MLK-9898 imx:mx6 fix ana2 offset of fuse bank1Peng Fan2014-11-24-0/+2
| | | | | | | | | | According to RM, there is 16bytes between offset ana1 and offset ana2. So should add 3 int hole 'u32 reserved[3]' between ana1 and ana2. Also add the reserved bytes for ana2 in this patch. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b0fd5f272895dfb0891872c099df7eef1519f729)
* MLK-9819: ARM: mx6sx: clear WDOG3 Power Down Enable bit for i.mx6sxRobin Gong2014-11-11-0/+4
| | | | | | | | | | | Since we use WDOG_B reset now, we have to clear WDOG3 Power Down Enable bit to avoid system reboot during normal kernel boot. For mx6sxsabresd board, we have to make sure pad setting for WDOG_B ready before mux ready, otherwise also cause reboot. But that dependes on hardware design, only need on mx6sxsabresd board. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 26875f93ac7e84748fa63e5f0dd948d12e663e43)
* MLK-9705 imx: mx6sx: Set the pad setting SION for I2C3 pinsYe.Li2014-10-20-2/+2
| | | | | | When set the pinmux to I2C functionality, the SION is required to enabled. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-9640 ARM: imx6sx: enable ldo-bypass on mx6sxsabresd boardRobin Gong2014-09-30-1/+1
| | | | | | enable ldo-bypass check on all mx6sxsabresd boards. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00332535 imx: mx6sx: Remove WEIM plugin work around for TO 1.2 and higherYe.Li2014-09-23-1/+7
| | | | | | | | ROM fixes the WEIM plugin issue in TO 1.2. The work around for hacking WEIM base address to ROM variable is not needed. To avoid hacking useful data, remove the work around for TO 1.2 and higher revisions. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331269 arm: mx6: select OSC as uart's clk parentAnson Huang2014-09-18-0/+9
| | | | | | | | As M4 is sourcing UART clk from OSC, to make UART work when M4 is enabled, need to select OSC as clk parent, 24M OSC is enough for debug UART in uboot. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00331706-4 imx: mx6sl: Set the preclk clock source to OSC 24MhzYe.Li2014-09-18-0/+16
| | | | | | | For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-3 imx: mx6: Change the get_ipg_per_clk for OSC 24Mhz sourceYe.Li2014-09-18-0/+4
| | | | | | | For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix the get_ipg_per_clk function to support it. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-2 imx: mx6sl: Add perclk_clk_sel bit define in CCMYe.Li2014-09-18-0/+2
| | | | | | | The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00331706-1 imx: gpt: Add 24Mhz OSC clock source support for GPTYe.Li2014-09-18-10/+66
| | | | | | | | | | | | | | | | Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will use 24Mhz OSC as clock source. Otherwise, the GPT will use 32Khz OSC as clock source. Since only the GPT on iMX6 series provide the clock source option for 24Mhz OSC. For other series(MX5), if the configuration is set, the perclk will be selected as clock source. MX6Q/D Rev 1.0 and MX6SL can't use the 24Mhz OSC clock source option, so select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00327364 iMX6: Ensure that the bandgap self-bias circuit is disabled ↵Ranjani Vaidyanathan2014-09-10-0/+24
| | | | | | | | | | | | after boot. The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00330792 imx: mx6: Merge anatop registers to CCM structureYe.Li2014-09-10-201/+144
| | | | | | | | | | THe anatop registers structure is duplicated with CCM structure at PLL fields. Since we are suggested not to use the name "anatop" any longer, merge the anatop registers to the CCM structure "mxc_ccm_reg" and use CCM to replace anatop. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLRPeng Fan2014-09-05-0/+3
| | | | | | | | | | This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00323255 Fixed QSPI randomly access timeout issueAllen Xu2014-08-29-16/+22
| | | | | | | | | | | | | | | | The QSPI clock rate was set without disabling the clock gate, the randomly glitch may mess up the clock and there will be no clock output, when kernel boot up the QSPI access will fail. To debug this issueon i.MX6SX SDB, changed the u-boot bootscript to 'sf probe; reset' to keep rebooting, the issue can be reproduced in 20 mins, set clock out register in CCM and measured TP86, found there is no clock ouput. To fix this bug, disable clock gate before changing clock rate. NOTICE: QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, need to disable both of them. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00329631: imx6: fix kernel suspend reboot if keep watchdog aliveRobin Gong2014-09-02-0/+5
| | | | | | | WDZST bit is write-once only bit. So we need take care the setting in kernel ,otherwise, kernel setting will never be enabled. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00326277-2 imx6: watchdog: use WDOG_B mode for wdog reset in ldo-bypass modeRobin Gong2014-08-26-2/+22
| | | | | | In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in ldo-bypass mode. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00326277-1: imx6: ldo_bypass: fix VDDARM voltage setting violate datasheetRobin Gong2014-08-26-2/+47
| | | | | | | | | Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo bypass switch. So untile ldo bypass switch happened, these voltage setting is set in ldo-enable mode. But in datasheet, we need 1.15V + 125mV = 1.275V for VDDARM_IN. We need to downgrade cpufreq to 400Mhz and restore after ldo bypass mode switch. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00328312 i2c: imx: Optimize the i2c device recovery solutionFugang Duan2014-08-25-2/+25
| | | | | | | | | | | | | | | From i2c spec, if device pull down the SDA line that causes i2c bus dead, host can send out 9 clock to let device release SDA. But for some special device like pfuze100, it pull down SDA line and the solution cannot take effort. The patch just add NACK and STOP signal after 8 dummy clock, and pmic can release SDA line after the recovery. Test case catch 375 times of i2c hang, and all are recovered. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before resetYe.Li2014-08-15-7/+16
| | | | | | | | | | | | | u-boot v2014 upstream codes have a problem in pfd reset (s_init function) that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by using dynamical cpu type checking and introducing two cpu types: MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform. Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00325255 pcie:enable pcie support on imx6sx sdRichard Zhu2014-07-31-7/+48
| | | | | | | | | | | | | | Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00322860 iMX6SX: Add function to check M4 status before bootingYe.Li2014-07-17-0/+14
| | | | | | | Add new function "arch_auxiliary_core_check_up" to check whether M4 is already up. Therefore, avoid starting M4 again when it is running. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00321435-1 imx-common: cpu: Disable mxsfb when necessaryLiu Ying2014-07-17-0/+4
| | | | | | | | The kernel may break the display pipeline at boot stage and introduce various display artifacts, so let's disable mxsfb in uboot when necessary. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* MX6: Correct calculation of PLL_SYSAndre Renaud2014-07-15-1/+1
| | | | | | | | DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do the shift after the multiply to avoid rounding errors Signed-off-by: Andre Renaud <andre@bluewatersys.com> (cherry picked from commit 2eb268f6fd236a5ad9d51e7e47190d7994b3920f)
* mx6: soc: Update the comments of set_ldo_voltage()Fabio Estevam2014-07-15-3/+2
| | | | | | | | | | | | | | | Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces set_ldo_voltage() function that can be used to set the voltages of any of the three LDO regulators controlled by the PMU_REG_CORE register. Prior to this commit there was a single set_vddsoc() which only configured the VDDSOC regulator. Update the comments to align with the new set_ldo_voltage() implementation. Acked-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> (cherry picked from commit 157f45da91b306d71dbf3a51325352dc11bf16d1)
* ENGR00321299 gis: clean csi0 input mux set bit in GPRSandor Yu2014-07-07-0/+6
| | | | | | | | When gis enable in uboot, the CSI0 input mux select setting to vadc module, clean the bit when gis disabled. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit ae66b17b7da3be50dc81ca636b67e8e879f52e26)
* ENGR00321260-1 iMX6: Add support to get CPU serial numberYe.Li2014-07-04-0/+13
| | | | | | | | The android boot needs get_board_serial function to get the CPU uid as the serial number. Implement this function to read the uid from fuse for all iMX6 platforms. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00320350 iMX6SLEVK: Fix build warning of PCIE Phy power downYe.Li2014-06-30-0/+2
| | | | | | | | | | | | Since the iMX6SL does not have PCIE module, should not define the function "imx_set_pcie_phy_power_down" for it. Otherwise, get the build warning below: arch/arm/cpu/armv7/mx6/soc.c:446:13: warning: 'imx_set_pcie_phy_power_down' defined but not used [-Wunused-function] static void imx_set_pcie_phy_power_down(void) Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00319965 pcie: mask the imx6sl outRichard Zhu2014-06-25-2/+7
| | | | | | | imx6sl doesn't have the pcie module, mask the pcie related codes from imx6sl. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00319415 pcie: random link down issue after warm-rstRichard Zhu2014-06-24-0/+18
| | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00319003 iMX6SX:HAB: Fixed build break when enabling secure bootYe.Li2014-06-18-2/+2
| | | | | | | | | | | | | | | When enabling "CONFIG_SECURE_BOOT", the build broken on iMX6SX platform due to two problems. 1. The imximage tool in v2014 changes the command name of "SECURE_BOOT" to "CSF". Must update it in imximage.cfg scripts. 2. The iMX6SX uses "CONFIG_ROM_UNIFIED_SECTIONS", but some HAB API definitions are not defined and cause compile errors. (HAB_RVT_REPORT_EVENT_NEW, HAB_RVT_REPORT_STATUS_NEW, HAB_RVT_AUTHENTICATE_IMAGE_NEW, HAB_RVT_ENTRY_NEW, HAB_RVT_EXIT_NEW) Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-81 gis: Add gis moduleYe.Li2014-06-17-0/+8
| | | | | | | | Add gis module, current gis is support vadc input. Add power down function to lcdif driver. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-77 mx6 soc: Add vadc power up/down functionYe.Li2014-06-17-0/+58
| | | | | | | Add vadc power up/down function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-76 mx6 clock: Add vadc clock enable functionYe.Li2014-06-17-0/+10
| | | | | | | Add vadc clock enable function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-71 iMX6SX Update registers and clock for displayYe.Li2014-06-17-1/+445
| | | | | | Add registers and clock functions to enable/set LCDIF clock and LVDS. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-70 iMX6SX:Video Update MXS LCDIF driverYe.Li2014-06-17-3/+3
| | | | | | | | | | | | Add a new interface "mxs_lcd_panel_setup" to setup fb parameters and specifies the LCDIF controller for multiple controllers of iMX6SX. Pass fb parameters via "videomode" env remains work if the new interface is not called before video initialization. Modify LCDIF clock interface "mxs_set_lcdclk" to support multiple LCDIF controllers on iMX6SX. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-59 iMX6SX: Add RDC mappings of masters and peripheralsYe.Li2014-06-17-0/+159
| | | | | | | Add the definitions for the RDC mappings on iMX6SX and include this file to "imx-rdc.h" Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-58 RDC: Add an iMX platform driver for RDC-SEMAYe.Li2014-06-17-0/+319
| | | | | | | | | | | | | | The RDC driver provides interfaces for setting peripherals and masters at BSP initialization, before using the peripherals driver. Another interfaces for lock/unlock RDC semaphore and permission check. The driver assumes boot CPU which runs u-boot is in Domain 0 (default setting on boot). Users should not set it to other domains. The peripherals ID and masters ID may change on different chip, each should provide definitions of the IDs and be included in "imx-rdc.h". Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-57 iMX6SX: Add M4 boot support at soc levelYe.Li2014-06-17-0/+30
| | | | | | | | | Implement the override function "arch_auxiliary_core_up" to boot Cortex-M4 by executing command "bootaux". The parameter "boot_private_data" points to fields where stores the stack address and PC address for M4 to run. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-55 iMX6SX: add debug monitor supportYe.Li2014-06-17-0/+29
| | | | | | | | | | | Debug monitor will print out last failed AXI access info when system reboot is caused by AXI access failure, only works when debug monitor is enabled. Enable this module on i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-54 iMX6SX/SL: Modify SOC to support two ENETYe.Li2014-06-17-5/+96
| | | | | | | | | | | | | | | | | | | | | iMX6SX has different enet system clocks with iMX6SL, and has two ENET controllers. So update clocks and soc APIs accordingly to support this features. 1. Modify the clock API "enable_enet_clock" to enable enet system clock for enet controllers. 2. Enet RGMII TX clock source may come from external or internal PLL. By default, use the external phy CLK_25M output as TX clock source. When using internal PLL as source, the function enable_fec_anatop_clock must be called to enable clock for each enet controller. 3. Modify the MAC address function "imx_get_mac_from_fuse" to get either ENET MAC address. 4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz reference clock. 5. Modify imx6slevk BSP to fit the new APIs. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-51 iMX6SX: Add QuadSPI clock enable functionYe.Li2014-06-17-0/+45
| | | | | | | Enable the clock for QuadSPI controllers. Must be called at initialization. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-48 iMX6SX: Add iMX6SX SoC supportYe.Li2014-06-17-17/+2149
| | | | | | | | | | | Adding clks, pinmux, memory map, etc for iMX6SoloX. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-44 imx6:USB: Update EHCI driver for OTG lines compatibilityYe.Li2014-06-17-12/+3
| | | | | | | | | | | To be compatible with more USB otg lines which has micro port B to connect imx6 OTG port when imx6 working at host mode, remove the checking for the OTG ID with the init type. Only use the init type for the power and controller initialization. Use same EHCI register base address for various imx6 platform. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-35 i.mx6: Fix issue in HAB clock settingYe.Li2014-06-17-9/+9
| | | | | | Should use the address of one register when calling "readl"/"writel". Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-19 iMX6 Disable the L2 before chaning the PL310 latencyYe.Li2014-06-17-0/+3
| | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. Setting these registers must have PL310 not enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. Thus, disable the PL310 before this setting. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-11 i.mx6:shutdown vddpu and pcie phy to save powerYe.Li2014-06-17-0/+31
| | | | | | | | shutdown vddpu and pcie phy to save power Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315499-21 HDMI: splash screen function enhancementNitin Garg2014-06-13-1/+11
| | | | | | | | | | | | -Change HDMI video mode to VGA. -Add pixel clock fraction part setting in IPU driver, fix video mode timing issue. -Add overflow state clear workaround, fix kernel hang in HDMI driver issue. -Correct IPU clock to 264MHz. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-17 ARM:imx6sl:evk Add SPI NOR flash boot and access supportNitin Garg2014-06-13-0/+5
| | | | | | | | | | | Add BSP codes to support SPI NOR flash read, write and erase by using "sf" command. In addition, add a new configuration "mx6slevk_spinor" for building the uboot that can be booted from SPI NOR flash and stored the environments variables in it. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-15 ARM:imx6sl:evk Add USB HOST supportNitin Garg2014-06-13-1/+4
| | | | | | | | Enable the USB EHCI for the imx6slevk board. Add VBUS control pin settings and related BSP codes. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* ENGR00315499-12: ARM: MSL: add i2c0 support for imx6sl evkNitin Garg2014-06-13-0/+5
| | | | | | | | - Add i2c0 support for imx6sl evk platform. - Read pmic device ID and revsion ID. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
generated by cgit v1.1 at 2024-11-19 10:06:24 +0000