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authorYe.Li <B37916@freescale.com>2014-06-06 16:38:53 +0800
committerYe.Li <B37916@freescale.com>2014-06-17 11:13:46 +0800
commit4b203b9895c0b39bf7a93c5fde59137952474126 (patch)
treee095c35ea98d4140c01278aba31cdcb87658eb95 /arch
parent66e7a93ff1e47d0e47627a984bcf2337db4f3bbf (diff)
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ENGR00315894-35 i.mx6: Fix issue in HAB clock setting
Should use the address of one register when calling "readl"/"writel". Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index fd6248d..625518a 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -505,16 +505,16 @@ void hab_caam_clock_enable(void)
u32 reg = 0;
/*CG4 ~ CG6, enable CAAM clocks*/
- reg = readl(ccm_regs->CCGR0);
+ reg = readl(&ccm_regs->CCGR0);
reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- writel(reg, ccm_regs->CCGR0);
+ writel(reg, &ccm_regs->CCGR0);
/* Enable EMI slow clk */
- reg = readl(ccm_regs->CCGR6);
+ reg = readl(&ccm_regs->CCGR6);
reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
- writel(reg, ccm_regs->CCGR6);
+ writel(reg, &ccm_regs->CCGR6);
}
void hab_caam_clock_disable(void)
@@ -523,16 +523,16 @@ void hab_caam_clock_disable(void)
u32 reg = 0;
/*CG4 ~ CG6, disable CAAM clocks*/
- reg = readl(ccm_regs->CCGR0);
+ reg = readl(&ccm_regs->CCGR0);
reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
- writel(reg, ccm_regs->CCGR0);
+ writel(reg, &ccm_regs->CCGR0);
/* Disable EMI slow clk */
- reg = readl(ccm_regs->CCGR6);
+ reg = readl(&ccm_regs->CCGR6);
reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
- writel(reg, ccm_regs->CCGR6);
+ writel(reg, &ccm_regs->CCGR6);
}
#endif