summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
...
| * | | sunxi: axp: Add driver-model support to the axp_gpio codeHans de Goede2015-05-04-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver-model support to the axp_gpio code, note that this needs a small tweak to the driver-model version of sunxi_name_to_gpio to deal with the vbus detect and enable pins which are not standard numbered gpios. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: axp: Move axp gpio code to a separate axpi-gpio driverHans de Goede2015-05-04-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the axp-gpio code out of the drivers/power/axp*.c code, and into a new separate axpi-gpio driver. This change drops supports for the gpio3 pin on the axp209, as that requires special handling, and no boards are using it. Besides cleaning things up by moving the code to a separate driver, as a bonus this change also adds support for the (non vusb) gpio pins on the axp221 and the gpio pins on the axp152. The new axp-gpio driver gets its own Kconfig option, and is only enabled on boards which need it. Besides that it only gets enabled in the regular u-boot build and not for the SPL as we never need it in the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: axp: Add support for i2c based PMICs to the pmic-bus helpersHans de Goede2015-05-04-8/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the axp152 and axp209 PMICs to the pmic register access helpers. This is a preparation patch for moving the axp gpio code to a separate gpio driver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: axp: Move axp pmic register helpers to a separate fileHans de Goede2015-05-04-0/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the register helpers used to access the registers via p2wi resp. rsb bus on the otherwise identical axp221 and axp223 pmics to a separate file, so that they can be used by the upcoming standalone axp gpio driver too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: usbc: Fix vbus gpio handling to work with the driver-modelHans de Goede2015-05-04-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver-model gpio functions may return another value then -1 as error, make the sunxi usbc properly handle this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Add basic A33 basic supportVishnu Patekar2015-05-04-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable full support for the A33 SoC including display, otg-usb, etc. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Add a33 dram init codeVishnu Patekar2015-05-04-0/+544
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Allwinner dram init code from the a33 bsp: https://github.com/allwinner-zh/bootloader/blob/master/basic_loader/bsp/bsp_for_a33/init_dram/mctl_hal.c Initial u-boot port by Vishnu Patekar, major cleanup / rewrite by Hans de Goede. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Add support for A33 PLL11 (second DRAM pll)Hans de Goede2015-05-04-3/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the new second DRAM PLL found on the A33 SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: s/sun8i/sun8i_a23/Hans de Goede2015-05-04-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch for adding A33 support, which will have a mach name of sun8i-a33. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Introduce a hidden SUNXI_GEN_SUNxI Kconfig boolHans de Goede2015-05-04-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i have a various things in common, like having separate ahb reset control registers, the SID living inside the pmic, custom pmic busses, new style watchdog, etc. This commit introduces a new hidden SUNXI_GEN_SUN6I Kconfig bool which can be used to check for these features avoiding the need for an ever growing list of "#if defined CONFIG_MACH_SUN?I" conditionals as we add support for more "new style" sunxi SoCs. Note that this commit changes the behavior of the gmac and hdmi code for sun8i and the upcoming sun9i devices. This does not matter as sun8i does not have gmac nor hdmi, and sun9i has new hardware-blocks for these so the old code will not work there. Also this is intentional as if a sun8i / sun9i variant which does use the old hwblocks shows up then the GEN_SUN6I code paths will be the right ones to use. For completeness this also adds a SUNXI_GEN_SUN4I bool for A10/A13/A20. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: usbc: Remove unused irq fieldHans de Goede2015-05-04-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not use irqs in u-boot so remove the unused irq field, and all the #ifdef-ery around the irq initialization. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sunxi: Also set Auxiliary Ctl SMP bit in SPLHans de Goede2015-05-04-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason not to and this make the #ifdef-ery easier to read. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun7i: Remove duplicate call to psci_arch_initJan Kiszka2015-05-02-1/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is already invoked a few cycles later in monitor mode by _secure_monitor (_sunxi_cpu_entry calls _do_nonsec_entry which triggers _secure_monitor via smc #0). Drop it here, it serves no purpose. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | x86: Enable multi-core init for Minnowboard MAXSimon Glass2015-04-30-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Enable the CPU uclass and Simple Firmware interface for Minnowbaord MAX. This enables multi-core support in Linux. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Add a CPU driver for baytrailSimon Glass2015-04-30-6/+227
| | | | | | | | | | | | | | | | | | | | | | | | This driver supports multi-core init and sets up the CPU frequencies correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Allow CPUs to be set up after relocationSimon Glass2015-04-30-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | This permits init of additional CPU cores after relocation and when driver model is ready. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Add functions to set and clear bits on MSRsSimon Glass2015-04-30-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | Since we do these sorts of operations a lot, it is useful to have a simpler API, similar to clrsetbits_le32(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Add multi-processor initSimon Glass2015-04-30-7/+934
| | | | | | | | | | | | | | | | | | | | | | | | | | | Most modern x86 CPUs include more than one CPU core. The OS normally requires that these 'Application Processors' (APs) be brought up by the boot loader. Add the required support to U-Boot to init additional APs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Provide access to the IDTSimon Glass2015-04-29-0/+7
| | | | | | | | | | | | | | | | | | | | | Add a function to return the address of the Interrupt Descriptor Table. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Store the GDT pointer in global_dataSimon Glass2015-04-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we start up additional CPUs we want them to use the same Global Descriptor Table. Store the address of this in global_data so we can reference it later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Add an mfence macroSimon Glass2015-04-29-0/+5
| | | | | | | | | | | | | | | | | | | | | Provide access to this x86 instruction from C code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Add defines for fixed MTRRsSimon Glass2015-04-29-0/+14
| | | | | | | | | | | | | | | | | | | | | Add MSR numbers for the fixed MTRRs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Add atomic operationsSimon Glass2015-04-29-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | Add a subset of this header file from Linux 4.0 to support atomic operations in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Add support for the Simple Firmware Interface (SFI)Simon Glass2015-04-29-0/+311
| | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a way of passing information to Linux without requiring the full ACPI horror. Provide a rudimentary implementation sufficient to be recognised and parsed by Linux. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Disable -WerrorSimon Glass2015-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is annoying during development and serves no useful purpose since warnings are clearly displayed now that we are using Kbuild. Remove this option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Remove unwanted MMC debuggingSimon Glass2015-04-29-1/+0
| | | | | | | | | | | | | | | | | | | | | This printf() should not have made it into the code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: fsp: Use reset_cpu()Simon Glass2015-04-29-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port on boards that use a Firmware Support Package (FSP). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: quark: Use reset_cpu()Simon Glass2015-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: ivybridge: Use reset_cpu()Simon Glass2015-04-29-15/+6
| | | | | | | | | | | | | | | | | | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: Implement reset_cpu() correctly for modern CPUsSimon Glass2015-04-29-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing code is pretty ancient and is unreliable on modern hardware. Generally it will hang. We can use port 0xcf9 to initiate reset on more modern hardware (say in the last 10 years). Update the reset_cpu() function to do this, and add a new 'full reset' function to perform a full power cycle. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | x86: link: Add PCH driver to support SPI FlashSimon Glass2015-04-29-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | U-Boot on coreboot does not have a driver for the PCH so cannot see the SPI peripheral now that it has moved inside the PCH. Add a simple driver so that SPI flash works again. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | x86: minnowmax: use the correct NOR in the configurationGabriel Huau2015-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SPI NOR on the minnowboard max is a MICRON N25Q064A Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Correct the typo in write_tables()Bin Meng2015-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | It should be #ifdef instead of #if. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/KconfigBin Meng2015-04-29-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | Since all x86 boards have been converted to use DM_SPI and DM_SPI_FLASH, move them to arch/Kconfig x86 section. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmeticsBin Meng2015-04-29-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also fix the indention of its help text. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Kconfig: Move platform options forwardBin Meng2015-04-29-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform-specific options under in arch/x86/Kconfig forward right after the board-specific options but before any architecture-specific options. When it comes to the same Kconfig option, board-specific one takes take the highest precedence, then platform-specific one, and finally architecture-specific one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Kconfig: Divide the target selection to vendor/modelBin Meng2015-04-29-79/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let arch/x86/Kconfig prompt board vendor first, then select the board model under that vendor. This way arch/x86/Kconfig only needs concern board vendor and leave the supported target list to board/<vendor>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: quark: Turn on legacy segments decodeBin Meng2015-04-29-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | By default the legacy segments (A0000h-B0000h, E0000h-F0000h) do not decode to system RAM. Turn on the decode so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Check PIRQ routing table sanity in the F segmentBin Meng2015-04-29-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the PIRQ routing table sanity check was performed against the original table provided by the platform codes. Now we switch to check its sanity on the final table in the F segment as this one is the one seen by the OS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: minnowmax: add GPIO banks in the device treeGabriel Huau2015-04-29-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: baytrail: fix the GPIOBASE addressGabriel Huau2015-04-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-4/+440
| | | | | | | | | | | | | | | | | | | | | | | | Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Support platform PIRQ routingBin Meng2015-04-29-0/+300
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Write configuration tables in last_stage_init()Bin Meng2015-04-29-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | We can write the configuration table in last_stage_init() for all x86 boards, but not with coreboot since coreboot already has them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Add a function to assign IRQ numbers to PCI deviceBin Meng2015-04-29-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function to assign an IRQ number to PCI device's interrupt line register in its configuration space, so that the PCI device can have its interrupt working under PIC mode after OS boots up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Install a default e820 table in the __weak install_e820_map()Bin Meng2015-04-29-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | Create a default e820 table with 3 entries which is enough to boot a Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Clean up arch/x86/include/asm/e820.hBin Meng2015-04-29-131/+2
| | | | | | | | | | | | | | | | | | | | | There are lots of unused codes defined in e820.h, clean it up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Add alias for SPI node in the board dtsBin Meng2015-04-29-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since Intel ICH SPI driver has been converted to driver model, we need add an alias for SPI node in the board dts files otherwise SPI flash won't be detected due to 'invalid bus' error. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Set serial port IRQ for SMSC LPC47MBin Meng2015-04-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | For starting a Linux console on the superio serial port under interrupt mode, the IRQ number must be configured. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: queensbay: Avoid using PCH prefixBin Meng2015-04-29-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prefix PCH was taken from ivybridge port. However Queensbay platform official document does not mention PCH. It is composed of TunnelCreek processor and Topcliff IOH chipset. For accuracy, avoid using PCH prefix in the macro. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-10 08:04:03 +0000