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* arm: Introduce setjmp/longjmpAlexander Graf2016-06-06-0/+99
| | | | | | | | | | | To quit an EFI application we will need logic to jump to the caller of a function without returning from the function we called into, so we need setjmp/longjmp functionality. This patch introduces a trivial implementation of these that I verified works on armv7, thumb2 and aarch64. Signed-off-by: Alexander Graf <agraf@suse.de>
* Fix to davinci_nand.h to place CEnCFG registers at correctPeter Howard2016-06-06-4/+6
| | | | Signed-off-by: Peter Howard <phoward@gme.net.au>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-06-06-1/+219
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| * ARM64: zynqmp: Extend page_table_sizeMichal Simek2016-06-06-0/+5
| | | | | | | | | | | | | | 0xc000 is not sufficient page table size if dc4 with 4 gems is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Add support for zc1751-dc4Michal Simek2016-06-06-0/+213
| | | | | | | | | | | | zc1751-dc4 contains four GEMs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * microblaze: Move MSR instruction selection to KconfigMichal Simek2016-06-06-1/+1
| | | | | | | | | | | | Select MSR instructions via Kconfig instead of xparameters.h. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm: lib: Fix fix push/pop-section directivesMarek Vasut2016-06-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Repair typos in the previous "arm: lib: fix push/pop-section directives" patch, which prevented VCMA9 board from building. Signed-off-by: Marek Vasut <marex@denx.de> Fixes: b2f1858455e9 ("arm: lib: fix push/pop-section directives") Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-06-04-14/+38
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| * | dm: test: Add GPIO open drain testsmario.six@gdsys.cc2016-06-03-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some tests for the new open drain setting feature of the GPIO uclass, and extend the capabilities of the sandbox GPIO driver accordingly. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | dm: gpio: Add driver for MPC85XX GPIO controllermario.six@gdsys.cc2016-06-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.Robert P. J. Day2016-06-03-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | Replace a number of array length calculations with the ARRAY_SIZE() macro, for clarity. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-04-4/+674
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| * | | armv8: ls1012a: Add support of ls1012afrdm boardPrabhakar Kushwaha2016-06-03-1/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls1012a: Add support of ls1012ardb boardPrabhakar Kushwaha2016-06-03-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls1012a: Add support of ls1012aqds boardPrabhakar Kushwaha2016-06-03-1/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Add support of QorIQ LS1012A SoCPrabhakar Kushwaha2016-06-03-0/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Organize SoC overview at common locationPrabhakar Kushwaha2016-06-03-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: fix compile warning "rcw_tmp"Prabhakar Kushwaha2016-06-03-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function ‘get_sys_info’: arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning: unused variable ‘rcw_tmp’ [-Wunused-variable] u32 rcw_tmp; Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Avoid LS1043A specifc definesPrabhakar Kushwaha2016-06-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant. So Avoid LS1043A specific defines in arch/arm Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Put SMMU config code in SMMU_BASEPrabhakar Kushwaha2016-06-03-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not mandatory for Layerscape SoCs to have SMMU. SoCs like LS1012A are layerscape SoC without SMMU IP. So put SMMU configuration code under SMMU_BASE. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-06-03-996/+211
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| * | ARM: tegra: add p2771-0000 board supportStephen Warren2016-05-31-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO expansion headers. Currently, due to U-Boot's level of support for Tegra186, the only features supported by U-Boot are the console UART and the on-board eMMC. Additional features will be added over time. U-Boot has so far been tested by replacing the kernel image on the device with a U-Boot binary. It is anticipated that U-Boot will eventually replace the CCPLEX bootloader binary, as on previous chips. This hasn't yet been tested. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add core Tegra186 supportStephen Warren2016-05-31-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the bare minimum code to support Tegra186, with UART and eMMC working. The empty gpio.h is required because <asm/gpio.h> includes it. A future cleanup round may be able to solve this for all Tegra generations at once. mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but instead to defer everything to mach-tegra/tegra186/Makefile. This allows the SoC code to pick-and-choose which of the C files in the "common" mach-tegra/ directory to compile in based on the SoC's needs. Most of the code is not valid for Tegra186, and this approach removes the need for mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach may be applied to all other Tegra SoCs in a future cleanup round. board186.c is introduced to replace board.c and board2.c. These files currently contain a slew of SoC- and board-specific code that is not valid for Tegra186. This approach avoids adding yet more ifdefs to those files. A future cleanup round may refactor most of board*.c into board-/ SoC-specific functions files thus allowing the top-level functions like board_init_early_f to be shared again. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: add basic Tegra186 supportStephen Warren2016-05-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186's MMC controller needs to be explicitly identified. Add another compatible value for it. Tegra186 will use an entirely different clock/reset control mechanism to existing chips, and will use standard clock/reset APIs rather than the existing Tegra-specific custom APIs. The driver support for that isn't ready yet, so simply disable all clock/reset usage if compiling for Tegra186. This must happen at compile time rather than run-time since the custom APIs won't even be compiled in on Tegra186. In the long term, the plan would be to convert the existing custom APIs to standard APIs and get rid of the ifdefs completely. The system's main eMMC will work without any clock/reset support, since the firmware will have already initialized the controller in order to load U-Boot. Hence the driver is useful even in this apparently crippled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: convert CONFIG_TEGRA_GPIO to KconfigStephen Warren2016-05-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Future chips will contain different GPIO HW. This change will enable future SoC support to select the appropriate GPIO driver for their HW, in a future-looking fashion, using Kconfig. TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all current Tegra chips used this GPIO HW) to simplify the later addition of support for Tegra SoCs that use different GPIO HW. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: use DT bindings for GPIO namingStephen Warren2016-05-31-996/+2
| |/ | | | | | | | | | | | | | | | | | | There are currently many places that define the list of all Tegra GPIOs; the DT binding header and custom Tegra-specific header file gpio.h. Fix the redundancy by replacing everything with the DT binding header file. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arm: lib: fix push/pop-section directivesStephen Warren2016-06-03-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the existing code, function symbols are defined in .text, and the body is defined in .text.xxx. This causes (at least some version of) the linker not to emit the function body into the final binary, since it's part of a different section to the symbols being referenced. This of course causes a wide variety of failures. This change moves the push/pop-section directives before the function symbols, and after any relate ENDPROC macro invocations, so that symbols and bodies are all in the "pushed" sections, and thus the function bodies are emitted into the binary. This solves (at least) the boot problems currently seen on Tegra systems that use SPL (i.e. all ARMv7 Tegras). Fixes: 13b0a91a6d48 ("arm: lib: Split asm symbols into different .text subsections") Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-06-02-1/+122
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| * | arm: socfpga: Add samtec VIN|ING boardMarek Vasut2016-06-01-1/+122
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
* | ARM: k2g: Configure reset mux to device resetLokesh Vutla2016-06-02-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM. Timer5(dedicated to ARM) when used as WatchDog timer, the events it generates are routed to the above mux. Following are the 3 events that can controlled bt the reset mux: - Device Reset - An interrupt to the ARM_GIC - An interrupt to the ARM_GIC followed by a device reset. Right now to give a default watchdog behaviour "Device reset" is being selected. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
* | arm: omap: Introduce vcores_init functionKeerthy2016-06-02-0/+12
| | | | | | | | | | | | | | | | The pmic registers for variants of am57xx boards are different hence we need to assign them carefully based on the board type. Add a function to assign omap_vcores after the board detection. Signed-off-by: Keerthy <j-keerthy@ti.com>
* | ARM: DRA7: Add macros for voltage values for all OPPsAnna, Suman2016-06-02-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Define specific macros for the voltage values for all voltage domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH. No separate macros are defined for VD_MPU and VD_CORE at OPP_OD and OPP_HIGH as these use the same values as OPP_NOM. The current macros will be used as common macros that can be redefined appropriately based on a selected OPP configuration at build time. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: DRA7: Consolidate voltage macros across different SoCsAnna, Suman2016-06-02-23/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | The voltage values for each voltage domain at an OPP is identical across all the SoCs in the DRA7 family. The current code defines one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x macros. Consolidate both these sets into a single set. This is done so as to minimize the number of macros used when voltage values will be added for other OPPs as well. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: DRA7: Define common macros for efuse register offsetsAnna, Suman2016-06-02-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage valuesAnna, Suman2016-06-02-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current OPP_NOM voltage values defined for the MPU and CORE voltage domains are based on the initial DRA75x_74x_SR1.1_DM data manual. As per this DM, the PMIC boot voltage can be set to either 1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE. While the current values are correct, the latter set of values are the values that are common across all DRA75x, DRA72x SoCs and for all current Silicon revisions. So, update both the MPU and CORE OPP_NOM voltages to 1.15V. The macros are also slightly reorganized so that both the MPU and CORE voltage domain values are defined together. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* | dra7xx: Enable USB_PHY3 32KHz clockRoger Quadros2016-06-02-2/+14
| | | | | | | | | | | | | | DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros <rogerq@ti.com>
* | ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAPRoger Quadros2016-06-02-2/+2
| | | | | | | | | | | | | | | | | | CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3 which is meant for gadget mode only. We need enable/disbale_usb_clocks() for host mode as well so provide for it. Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks" Signed-off-by: Roger Quadros <rogerq@ti.com>
* | arm: lib: Split asm symbols into different .text subsectionsMarek Vasut2016-06-02-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | Split each symbol in lib1funcs into different .text.foo section instead of placing all of them into plain .text . This allows the linker to collect and discard unused assembler symbols. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: Import Thumb1 functionsMarek Vasut2016-06-02-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Import functions into lib1funcs.S which are required for Thumb1 build. These functions come from gcc 5.3.1 release. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: import muldi3.S from LinuxMarek Vasut2016-06-02-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import muldi3.S from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 on arm32. This file implements __aeabi_lmul and it's alias __muldi3, which is needed when doing Thumb1 builds. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: Repair Warning: conditional infixes are deprecated in unified syntaxMarek Vasut2016-06-02-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following warning when building for thumb2 target by tweaking the instruction syntax: Warning: conditional infixes are deprecated in unified syntax Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: Import __do_div64 from LinuxMarek Vasut2016-06-02-1/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import __do_div64 from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 on arm32. This function is for some toolchains, which generate _udivmoddi4() for 64 bit division. Since we do not support stack unwinding, instead of importing the whole asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: Fix uldivmod.S build on Thumb2Marek Vasut2016-06-02-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This assembler source won't build in Thumb2 mode, so fix it adding the necessary Thumb2 conditional macros from unified.h . This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: Sync libgcc 32b division/modulo operationsMarek Vasut2016-06-02-430/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these four files are present in lib1funcs.S in Linux, so replace these files with lib1funcs.S from Linux. Since we do not support stack unwinding, instead of importing the whole asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro in lib1funcs.S . Moreover, to make all of the functions available, define CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM EABI. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: Sync libgcc shift operationsMarek Vasut2016-06-02-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the libgcc shift operations with Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three files is easy, as there is almost no change in them, except the addition of Thumb support. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: lib: Drop underscore from private libgcc filenamesMarek Vasut2016-06-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Drop the underscore from the filenames of files implementing libgcc routines. There is no functional change. This change is done to make sync with Linux kernel easier. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: include: Import unified.h from Linux kernelMarek Vasut2016-06-02-7/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import unified.h from Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains macros used in libgcc functions in Linux kernel on ARM and will be needed for the libgcc sync. Since unified.h defines the W(instr) macro, we must drop this from the macro from memcpy.S , otherwise this triggers a warning about symbol redefinition. In order to keep the changes to unified.h to the minimum, tweak arch/arm/lib/Makefile such that it defines the CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all of the assembler files. This is mandatory. Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and only if Thumb2 build is enabled. This macro is checked by unified.h and toggles between ARM and Thumb2 variant of the instructions in the assembler source files. Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between more optimal and more dense codepaths which work on armv5 and newer and less optimal codepaths which work on armv4 and possible armv3m. Tegra2 needs the same special handling as it does in arch/arm/Makefile to cater for the arm720t boot core. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: config: Introduce CONFIG_SYS_ARM_ARCHMarek Vasut2016-06-02-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce new helper Kconfig option, which is automatically set to the version of ARM architecture for which the U-Boot is built. This is useful when selecting tuning options in the libgcc imported from Linux kernel. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: Select CONFIG_ARM64 for Cavium ThunderXMarek Vasut2016-06-02-0/+1
| | | | | | | | | | | | | | | | Select the config option, since this board is ARM64. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* | arm: Treat arm946es as v5teMarek Vasut2016-06-02-1/+1
|/ | | | | | | | The arm946es is armv5te , so use -march=armv5te instead of armv4t. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-05 17:02:59 +0000