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* drivers: usb: musb: adopt musb backend driver to driver modelMugunthan V N2016-12-02-11/+12
| | | | | | | | | | Currently all backend driver ops uses hard coded physical address, so to adopt the driver to DM, add device pointer to ops call backs so that drivers can get physical addresses from the usb driver priv/plat data. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* am33xx: board: probe misc drivers to register musb devicesMugunthan V N2016-12-02-0/+7
| | | | | | | | | MUSB wrapper driver is bound as MISC device and underlying usb devices are bind to usb drivers based on dr_mode, so probing the MISC wrapper driver to register musb devices. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* am33xx: board: do not register usb devices when CONFIG_DM_USB is definedMugunthan V N2016-12-02-1/+4
| | | | | | | Do not register usb devices when CONFIG_DM_USB is define. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORYMasahiro Yamada2016-12-02-6/+25
| | | | | | | | | | | | | | | | | | Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option") allows us to skip memory setup of DTB, but a problem for ARM is that spin_table_update_dt() and psci_update_dt() are skipped as well if CONFIG_ARCH_FIXUP_FDT is disabled. This commit allows us to skip only fdt_fixup_memory_banks() instead of the whole of arch_fixup_fdt(). It will be useful when we want to use a memory node from a kernel DTB as is, but need some fixups for Spin-Table/PSCI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for x86: Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: mvebu: move SYS_MVEBU_PLL_CLOCK to KconfigChris Packham2016-12-01-3/+6
| | | | | | | | | | The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x. [ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-11-30-63/+582
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| * MIPS: Fix map_physmem for cached mappingsPaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | map_physmem should return a pointer that can be used by the CPU to access the given memory - on MIPS simply returning the physical address as it does prior to this patch doesn't achieve that. Instead return a pointer to the memory within (c)kseg0, which matches up consistently with the (c)kseg1 pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use ram_top, not bi_memsize, in arch_lmb_reservePaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | When calculating the region to reserve for the stack in arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough memory to reach the end of the address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * mips: Let cache.h be included from assembly sourceMarek Vasut2016-11-30-0/+2
| | | | | | | | | | | | | | | | | | Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck2016-11-30-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: reserve space for exception vectorsDaniel Schwierzeck2016-11-30-0/+20
| | | | | | | | | | | | | | | | | | | | | | In order to set own exception handlers, a table with the exception vectors must be built in DRAM and the CPU EBase register must be set to the base address of this table. Reserve the space above the stack and use gd->irq_sp as storage for the exception base address. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add asm-offsets for struct pt_regsDaniel Schwierzeck2016-11-30-0/+66
| | | | | | | | | | | | | | Import asm-offsets.c from kernel to generate offset for struct pt_regs needed by exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck2016-11-30-0/+18
| | | | | | | | | | | | | | | | | | | | This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: factor out code for initial stack and global dataDaniel Schwierzeck2016-11-30-26/+30
| | | | | | | | | | | | | | Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck2016-11-30-24/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix ROM exception vectorsDaniel Schwierzeck2016-11-30-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck2016-11-30-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-11-30-54/+174
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| * imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)Lukasz Majewski2016-11-30-0/+15
| | | | | | | | | | | | | | | | This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
| * mx6sx: Add initial support for Samtec VIN|ING 2000 boardChristoph Fritz2016-11-30-0/+7
| | | | | | | | | | | | | | | | This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marex@denx.de>
| * mx6sx: Add initial support for UDOO Neo BoardBreno Lima2016-11-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte@gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: ts4600: add basic board supportSebastien Bourdelin2016-11-29-0/+6
| | | | | | | | | | | | | | | | This commit adds basic support including: MMC, Serial console Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson2016-11-29-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: add routine to return DDR calibration dataEric Nelson2016-11-29-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: pass mx6_ddr_sysinfo to calibration routinesEric Nelson2016-11-29-44/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * mx6: ddr: allow 32 cycles for DQS gating calibrationEric Nelson2016-11-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * imx: mx6: ddr: add register MPZQLP2CTL for LPDDR2Eric Nelson2016-11-29-0/+2
| | | | | | | | | | | | | | | | | | Add constants for the MPZQLP2CTL DDR register for both banks to allow setting the LPDDR2 timing values in .cfg files using a named constant instead of hex addresses as is currently done in mx6slevk and other board files. Signed-off-by: Eric Nelson <eric@nelint.com>
| * imx: make ipu's di configurableMax Krummenacher2016-11-29-1/+2
| | | | | | | | | | | | | | | | | | The ipu has two display interfaces. Make the used one a parameter in struct display_info_t instead of using unconditionally DI0. DI0 is the default setting. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Eric Nelson <eric@nelint.com>
| * ARM: mx6: add MMC2 boot device detection support in SPLMarcin Niestroj2016-11-29-1/+5
| | | | | | | | | | | | | | | | | | Check BOOT_CFG2[3:4] to determine which SD/MMC port is selected to boot from. If MMC2 is selected return BOOT_DEVICE_MMC2. In all other cases return BOOT_DEVICE_MMC1, as we do not have corresponding macro for MMC3 and MMC4. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-11-29-426/+2989
| |\ | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: update the REFTOP_VBGADJ settingPeng Fan2016-11-16-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
| * | imx: mx6sx: Disable ENET clock before switching clock parentYe.Li2016-11-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Need to gate ENET clock when switching to a new clock parent, because the mux is not glitchless. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-11-29-381/+545
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| * | | powerpc: Drop default CONFIG_MAX_CPUSYork Sun2016-11-23-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This configuration has been moved into Kconfig for mpc85xx, and dropped for mpc86xx. Remove the default value in config.h. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: mpc86xx: Remove macro CONFIG_MAX_CPUSYork Sun2016-11-23-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | This macro CONFIG_MAX_CPUS is not used for MPC86xx SoCs. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: MPC8641: Remove macro CONFIG_MPC8641York Sun2016-11-23-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace CONFIG_MPC8641 with ARCH_MPC8641 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: MPC8610: Remove macro CONFIG_MPC8610York Sun2016-11-23-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace CONFIG_MPC8610 with ARCH_MPC8610 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: mpc85xx: Move CONFIG_MAX_CPUS to KconfigYork Sun2016-11-23-43/+36
| | | | | | | | | | | | | | | | | | | | | | | | Use Kconfig to set MAX_CPUS for mpc85xx. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T4080: Drop configuration for T4080York Sun2016-11-23-17/+7
| | | | | | | | | | | | | | | | | | | | | | | | There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T4240: Remove macro CONFIG_PPC_T4240York Sun2016-11-23-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T4160: Remove macro CONFIG_PPC_T4160York Sun2016-11-23-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T4160RDB: Separate from T4240RDB in KconfigYork Sun2016-11-23-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Use TARGET_T4160RDB to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T4240QDS: Remove macro CONFIG_T4240QDSYork Sun2016-11-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_TARGET_T4240QDS instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T4160QDS: Separate from T4240QDS in KconfigYork Sun2016-11-23-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | Use TARGET_T4160QDS to simplify Kconfig options. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081York Sun2016-11-23-18/+27
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T2080RDB: Rename from T208XRDB in KconfigYork Sun2016-11-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | T208XRDB only has one target T2080RDB. Use TARGET_T2080RDB in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T208XQDS: Split as T2080QDS and T2081QDSYork Sun2016-11-23-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | Use two separated targets in Kconfig to simplify configurations. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDBYork Sun2016-11-23-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI. CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T1042D4RDB: Separate from T1042RDB in KconfigYork Sun2016-11-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use TARGET_T1042D4RDB in Kconfig to simplify config options. Remove macro CONFIG_T1042D4RDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * | | powerpc: T1042RDB_PI: Split from T1042RDB in KconfigYork Sun2016-11-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use separated TARGET_T1042RDB_PI to simplify config options. Remove macro CONFIG_T1042RDB_PI. Signed-off-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-09-12 21:52:04 +0000