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author | York Sun <york.sun@nxp.com> | 2016-11-21 13:35:41 -0800 |
---|---|---|
committer | York Sun <york.sun@nxp.com> | 2016-11-23 23:42:15 -0800 |
commit | 26bc57da0ac1ed5769e53b0ef561fd4f08c020c7 (patch) | |
tree | a6e6b3d40c3c3b29b8500aa7788eaa1842ef8567 /arch | |
parent | 652a7bbd87d322c49ffe138b98563dc6c8cd2885 (diff) | |
download | u-boot-imx-26bc57da0ac1ed5769e53b0ef561fd4f08c020c7.zip u-boot-imx-26bc57da0ac1ed5769e53b0ef561fd4f08c020c7.tar.gz u-boot-imx-26bc57da0ac1ed5769e53b0ef561fd4f08c020c7.tar.bz2 |
powerpc: T4240: Remove macro CONFIG_PPC_T4240
Use CONFIG_ARCH_T4240 from Kconfig instead.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 5 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 4 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 4 |
7 files changed, 15 insertions, 10 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 991127d..83dd1e0 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -274,11 +274,13 @@ config TARGET_T4160RDB config TARGET_T4240QDS bool "Support T4240QDS" + select ARCH_T4240 select SUPPORT_SPL select PHYS_64BIT config TARGET_T4240RDB bool "Support T4240RDB" + select ARCH_T4240 select SUPPORT_SPL select PHYS_64BIT @@ -424,6 +426,9 @@ config ARCH_T2081 config ARCH_T4160 bool +config ARCH_T4240 + bool + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index cf2aaa1..e5b45e1 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -44,7 +44,7 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o obj-$(CONFIG_ARCH_P4080) += p4080_ids.o obj-$(CONFIG_ARCH_P5020) += p5020_ids.o obj-$(CONFIG_ARCH_P5040) += p5040_ids.o -obj-$(CONFIG_PPC_T4240) += t4240_ids.o +obj-$(CONFIG_ARCH_T4240) += t4240_ids.o obj-$(CONFIG_ARCH_T4160) += t4240_ids.o obj-$(CONFIG_PPC_T4080) += t4240_ids.o obj-$(CONFIG_ARCH_B4420) += b4860_ids.o @@ -86,7 +86,7 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o -obj-$(CONFIG_PPC_T4240) += t4240_serdes.o +obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o obj-$(CONFIG_PPC_T4080) += t4240_serdes.o obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 9fab8ed..9d81873 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -511,7 +511,7 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif -#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_PPC_T4240) || \ +#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \ defined(CONFIG_ARCH_T4160) || defined(CONFIG_PPC_T4080) void fdt_fixup_dma3(void *blob) { @@ -529,7 +529,7 @@ void fdt_fixup_dma3(void *blob) case 0x29: case 0x2d: case 0x2e: -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ +#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS4_PRTCL; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e4feb3f..7f10ed0 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -130,7 +130,7 @@ void get_sys_info(sys_info_t *sys_info) * it uses 6. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \ defined(CONFIG_ARCH_T2081) svr = get_svr(); diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 4b73e76..1a5bcb1 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -15,7 +15,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index fc8e011..0d8eb46 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -545,7 +545,7 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ +#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ @@ -553,7 +553,7 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#ifdef CONFIG_PPC_T4240 +#ifdef CONFIG_ARCH_T4240 #define CONFIG_MAX_CPUS 12 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 19ce7f3..75868fa 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,7 +1759,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 @@ -1875,7 +1875,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \ +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 |