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| * imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan2015-08-02-34/+49
| | | | | | | | | | | | | | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: add cpu type for i.MX6QP/DPPeng Fan2015-08-02-5/+16
| | | | | | | | | | | | | | | | | | | | | | Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-627/+1798
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| * | i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-10-4/+15
| | | | | | | | | | | | | | | | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | iMX: adding parsing to hab_status commandUlises Cardenas2015-07-10-13/+245
| | | | | | | | | | | | | | | | | | | | | | | | hab_status command returns a memory dump of the hab event log. But the raw data is not human-readable. Parsing such data into readable event will help to minimize debbuging time. Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
| * | imx: mx6 add i2c4 clock support for i.MX6SXPeng Fan2015-07-10-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C4 clock support for i.MX6SX. Since we use runtime check, but not macro, we need to remove `#ifdef ..` in crm_regs.h, or gcc will fail to compile the code succesfully. Making the macros only for i.MX6SX open to other i.MX6x maybe not a good choice, but we have runtime check. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | imx: mx6 remove duplicated enable_cspi_clockPeng Fan2015-07-10-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable_spi_clock does the same thing with enable_cspi_clock, so remove enable_cspi_clock. Remove enable_cspi_clock prototype in header file convert cm_fx6/spl.c to use enable_spi_clk Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-07-31-58/+89
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| * | | powerpc/t4240: update serdes tableShaohui Xie2015-07-31-55/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3 support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes A/B/C/D are not available, updated the serdes table accordingly with some minor fix. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAMAneesh Bansal2015-07-31-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041Aneesh Bansal2015-07-31-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025Nikhil Badola2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1 for p1025 as it has one USB controller Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t1024: update fman liodn for mac1Shengzhou Liu2015-07-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have same Port ID and same offset of address with 1G MAC. Update it to match with the setting of fman in t1024 device tree, otherwise there is no 'fsl,liodn' in /proc/device-tree/soc@ffe000000/fman@400000/port@88000/ Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/T104xD4: Add Secure boot support for T104xD4RDB platformsgaurav rana2015-07-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu2015-07-31-10/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-07-29-64/+3567
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| * | | | T210: Add support for 64-bit T210-based P2571 boardTom Warren2015-07-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | P2571: dts: Add DT file for Tegra210 P2571 boardTom Warren2015-07-28-1/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on T124 Venice2. SDMMC1 is SD-card slot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-39/+453
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+2933
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | Tegra: Rework KConfig options to allow 64-bit builds (T210)Tom Warren2015-07-28-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will require a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | Tegra210: Fix 64-bit build warning about save_boot_params_ret()Tom Warren2015-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simon's 'tegra124: Implement spl_was_boot_source()' needs a prototype for save_boot_params_ret() to build cleanly for 64-bit Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: Initialize timer earlierThierry Reding2015-07-28-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A subsequent patch will enable the use of the architected timer on ARMv8. Doing so implies that udelay() will be backed by this timer implementation, and hence the architected timer must be ready when udelay() is first called. The first time udelay() is used is while resetting the debug UART, which happens very early. Make sure that arch_timer_init() is called before that. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: Use standard cache enable for 64-bitThierry Reding2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 64-bit SoCs the I-cache isn't enabled in early code, so the default cache enable functions for 64-bit ARM can be used. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCsThierry Reding2015-07-28-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | armv8/cache: Fix page table creationThierry Reding2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While generating the page tables, a running integer index is shifted by SECTION_SHIFT (29) and causes overflow for any integer bigger than 7. The page tables therefore alias to the same 8 sections and cause U-Boot to hang once the MMU is enabled. Fix this by making the index a 64-bit unsigned integer and so avoid the overflow. swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and "j" varies depending on RAM size; from 4 to 11 for a board with 4GB at physical address 2GB, as some Tegra boards have. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding2015-07-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | ARM: tegra: Build warning fixes for 64-bitThierry Reding2015-07-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, stripped out changes not strictly related to warnings] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | tegra124: Implement spl_was_boot_source()Simon Glass2015-07-27-0/+16
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of this function for Tegra. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | x86: Reserve PCIe ECAM address range in the E820 tableBin Meng2015-07-28-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should mark PCIe ECAM address range in the E820 table as reserved otherwise kernel will not attempt to use ECAM. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: qemu: Turn on PCIe ECAM address range decoding on Q35Bin Meng2015-07-28-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Turn on PCIe ECAM address range decoding on Q35. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: qemu: Enable writing MP tableBin Meng2015-07-28-3/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable writing MP table for QEMU boads (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Allow cpu-x86 driver to be probed for UPBin Meng2015-07-28-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently cpu-x86 driver is probed only for SMP. We add the same support for UP when there is only one cpu node in the deive tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: qemu: Enable I/O APIC chip select on PIIX3Bin Meng2015-07-28-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PIIX3 chipset does not integrate an I/O APIC, instead it supports connecting to an external I/O APIC which needs to be enabled manually. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: mpspec: Move writing ISA interrupt entry after PCIBin Meng2015-07-28-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms the I/O APIC interrupt pin#0-15 may be connected to platform pci devices' interrupt pin. In such cases the legacy ISA IRQ is not available so we should not write ISA interrupt entry if it is already occupied. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APICBin Meng2015-07-28-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently during writing MP table I/O interrupt assignment entry, we assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which however is not always the case on some platforms. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Convert to use driver model pci on queensbay/crownbayBin Meng2015-07-28-53/+5
| | | | | | | | | | | | | | | | | | | | | | | | Move to driver model pci for Intel queensbay/crownbay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | | | x86: pci: Do not assign irq 0 to pci deviceBin Meng2015-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | IRQ 0 is reserved and should not be assigned to pci device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: pci: Assign pci irqs to all functionsBin Meng2015-07-28-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need walk through all functions within a PCI device and assign their IRQs accordingly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-28-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
* | | | x86: Change pci option rom area MTRR setting to cacheableBin Meng2015-07-28-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Turn on cache on the pci option rom area to improve the performance. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Simplify architecture defined exception handling in irq_llsr()Bin Meng2015-07-28-105/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using switch..case for architecture defined exceptions, simply unify the handling by printing a message of exception name, followed by registers dump then halt the CPU. With this unification, it also fixes the wrong exception numbers for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Display correct CS/EIP/EFLAGS when there is an error codeBin Meng2015-07-28-4/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some exceptions cause an error code to be saved on the current stack after the EIP value. We should extract CS/EIP/EFLAGS from different position on the stack based on the exception number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-07-28-62/+1238
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| * | | | ARM: zynqmp: Wire up SATA for the boardMichal Simek2015-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SATA for the ZynqMP targets. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynqmp: Wire up ethernet controllersMichal Simek2015-07-28-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wire up ethernet controllers and enable MII and BOOTP options. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: Add support for zc770-xm011Michal Simek2015-07-28-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add xm011 DTS file and related configs and configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Update zc770 dtsesMichal Simek2015-07-28-12/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platform DTSes are missing content needed for platform to be able to use OF binding and DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keysMichal Simek2015-07-28-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the two MIO connected pushbuttons on the zc702 board to the devicetree as a single multi-key device for us with the gpio-keys driver. Signed-off-by: Ezra Savard <ezra.savard@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: DT: Add missing interrupt for L2 pl310Michal Simek2015-07-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-10-24 10:29:18 +0000