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| * | | net: keystone_net: register eth PHYs on MDIO busKhoronzhuk, Ivan2014-10-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As MDIO bus has been added we can register PHYs with it. After registration, the PHY driver will be probed according to the hardware on board. Startup PHY at the ethernet open. Use phy_startup() instead of keystone_get_link_status() when eth open, as it verifies PHY link inside and SGMII link is checked before. For K2HK evm PHY configuration at init was absent, so don't enable phy config at init for k2hk evm. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | soc: keystone_serdes: generalize to be used by other sub systemsHao Zhang2014-10-23-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes driver is used by other sub systems like PCI, sRIO etc. So modify it to be more general. The SerDes driver provides common API's that can also be extended for other peripherals SerDes configurations. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurationsHao Zhang2014-10-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the driver to use cmu/comlane/lane specific configurations instead of 1 big array of configuration. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | soc: keystone_serdes: create a separate SGMII SerDes driverKhoronzhuk, Ivan2014-10-23-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: increase MDIO clock frequencyVitaly Andrianov2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With MAC_PHY sgmii configuration, u-boot checks PHY link status before sending each packet. Increasing MDIO frequency increases overall tftp speed. We set it to maximum 2.5MHz. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: move header file from arch to ti-commonKhoronzhuk, Ivan2014-10-23-256/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: add support for NETCP v1.5Khoronzhuk, Ivan2014-10-23-62/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the network driver is used only by k2hk evm board. The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e contain NETCP v1.5. So driver should be able to work with such kind of NETCP. This commit adds this opportunity. The main difference in masks and some registers, the logic is the same, so only definitions should be changed. To differentiate between versions add KS2_NETCP_V1_0 and KS2_NETCP_V1_5. Also remove unused and no more needed defines. The port number is specific for each board so move this parameter to configuration. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_net: remove SoC specific emac_regs structureHao Zhang2014-10-23-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes K2HK SOC specifc emac_regs structure, it uses soc specific register offset to keep the network driver common across all the Keystone II EVMs. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: k2l-evm: add board supportHao Zhang2014-10-23-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone II Lammar (K2L) EVM board support. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: enable OSR clock domain for K2L SoCHao Zhang2014-10-23-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches enables the On-chip Shared Ram clock domain for K2L SoC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: keystone2: spl: move board specific codeHao Zhang2014-10-23-66/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization of PLLs is a part of board specific code, so move it appropriate places. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: msmc: add MSMC cache coherency support for K2L SOCHao Zhang2014-10-23-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds Keystone II Lamar (K2L) SoC specific definitions to support MSMC cache coherency. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: clock: add K2L clock definitions and commandsHao Zhang2014-10-23-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock definitions and commands to support Keystone II K2L SOC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: keystone2: add K2L device hardware definitionsHao Zhang2014-10-23-2/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hardware definitions specific to Keystone II Lamar (K2L) SoC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: cmd_clock: generalize command usage descriptionKhoronzhuk, Ivan2014-10-23-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usage description of commands refers to headers of sources, that is not correct. This patch is intended to fix it. Also generalize code in order to reduce SoC dependent #ifdefs. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone: usb: add support of usb xhciWingMan Kwok2014-10-23-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | dma: keystone_nav: generalize driver usageKhoronzhuk, Ivan2014-10-23-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | dma: keystone_nav: move keystone_nav driver to driver/dma/Khoronzhuk, Ivan2014-10-23-355/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The keystone_nav is used by drivers/net/keystone_net.c driver to send and receive packets, but currently it's placed at keystone arch sources. So it should be in the drivers directory also. It's separate driver that can be used for sending and receiving pktdma packets by others drivers also. This patch just move this driver to appropriate directory and doesn't add any functional changes. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: keystone_nav: don't use hard addresses in netcp_pktdmaKhoronzhuk, Ivan2014-10-23-29/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use definitions in netcp_pktdma instead direct addresses. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | keystone2: keystone_nav: don't use hard addresses in qm_configKhoronzhuk, Ivan2014-10-23-32/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use definitions in qm_config. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-10-27-26/+2
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| * | | arm: socfpga: Zap spl.h and ad-hoc related symsMarek Vasut2014-10-27-25/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the common spl.h file and zap the arch/spl.h . Since the arch/spl.h contained various ad-hoc symbols, zap those symbols as well and rework the board configuration a little so it doesn't depend on them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
| * | | arm: socfpga: Move code from misc_init_r() to arch_early_init_r()Marek Vasut2014-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this initialization code to proper place. The misc_init_r() function is called way too late and the platform initialization code should be executed much earlier. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Pavel Machek <pavel@denx.de>
* | | | Merge http://git.denx.de/u-boot-sunxiTom Rini2014-10-26-41/+749
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| * | | | sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig optionHans de Goede2014-10-24-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig option which users can select when they want to boot older kernels, e.g. the linux-sunxi 3.4 kernels. For now this just forces the pll5 "p" value to 1 (divide by 2) as that is what those kernels are hardcoded too, in the future this may enable further workarounds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@ti.com> -- Changes in v2: -s/CONFIG_OLD_KERNEL_COMPAT/CONFIG_OLD_SUNXI_KERNEL_COMPAT. -Move the code block setting P(1) for old kernels to where P gets cleared
| * | | | sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcodingHans de Goede2014-10-24-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Add clock_get_pll5p() functionHans de Goede2014-10-24-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add support for using R_UART as consoleChen-Yu Tsai2014-10-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads. Add support for R_UART so we can have a console while using mmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Allow specifying module in prcm apb0 init functionChen-Yu Tsai2014-10-24-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add support for R_PIO gpio banksHans de Goede2014-10-24-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond. Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] [wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add basic A23 supportChen-Yu Tsai2014-10-24-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup. There is no SPL support for A23, as we do not have any documentation or sample code for DRAM initialization. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | mmc: sunxi: Add support for sun8i (A23)Chen-Yu Tsai2014-10-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i. Re-use code added for sun6i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add support for uart0 on port F (mmc0)Chen-Yu Tsai2014-10-24-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add sun8i (A23) UART0 pin mux supportChen-Yu Tsai2014-10-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART0 pin muxes on the A23 have a different function value. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Fix reset command on sun6i/sun8iChen-Yu Tsai2014-10-24-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The watchdog on sun6i/sun8i has a different layout. Add the new layout and fix up the setup functions so that reset works. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk> [ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
| * | | | ARM: sunxi: Add sun6i/sun8i timer block register definitionChen-Yu Tsai2014-10-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RTC hardware has been moved out of the timer block on sun6i/sun8i. In addition, there are more watchdogs available. Also note that the timer block definition is not completely accurate for sun5i/sun7i. Various blocks are missing or have been moved out. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Move watchdog register definitions to separate fileChen-Yu Tsai2014-10-24-14/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On later Allwinner SoCs, the watchdog hardware is by all means a separate hardware block, with its own address range and interrupt line. Move the register definitions to a separate file to facilitate supporting newer SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: Use PG3 - PG8 as io-pins for mmc1Hans de Goede2014-10-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | None of the known sunxi devices actually use mmc1 routed through PH, where as some devices do actually use mmc1 routed through PG, so change the routing of mmc1 to PG. If in the future we encounter devices with mmc1 routed through PH, we will need to change things to be a bit more flexible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | sunxi: When we've both mmc0 and mmc2, detect from which one we're bootingHans de Goede2014-10-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're booting, and make that one "mmc dev 0" so that a single u-boot binary can be used for both the onboard eMMC and for external sdcards. When we're booting from mmc2, we make it dev 0 because that is where the SPL will load the tertiary payload (the actual u-boot binary in our case) from, see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Add basic A31 supportMaxime Ripard2014-10-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new sun6i machine that supports UART and MMC. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef around mmc and smp code, drop MACH_TYPE] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sun6i: Setup the A31 UART0 muxingMaxime Ripard2014-10-24-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] [wens@csie.org: reorder #ifs by SUN?I] [wens@csie.org: replace magic numbers with GPIO definitions] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sun6i: Define UART0 pins for A31Chen-Yu Tsai2014-10-24-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UART0 is the default debug/console UART on the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi-mmc: Add mmc support for sun6i / A31Hans de Goede2014-10-24-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmc hardware on sun6i has an extra reset control that needs to be de-asserted prior to usage. Also the FIFO address is different. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use setbits_le32 for reset control, drop obsolete changes, rewrite different FIFO address handling, add commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sun6i: Add clock supportChen-Yu Tsai2014-10-24-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the basic clocks support for the Allwinner A31 (sun6i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. This includes changes from the following commits from u-boot-sunxi: a92051b ARM: sunxi: Add sun6i clock controller structure 1f72c6f ARM: sun6i: Setup the UART0 clocks 5f2e712 ARM: sunxi: Enable pll6 by default on all models 2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31 12e1633 ARM: sun6i: Add initial clock setup for SPL 1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code 0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe b54c626 sunxi: avoid sr32 for APB1 clock setup. 68fe29c sunxi: remove magic numbers from clock_get_pll{5,6} c89867d sunxi: clocks: clock_get_pll5 prototype and coding style 501ab1e ARM: sunxi: Fix sun6i PLL6 settings 37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets 61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: styling fixes reported by checkpatch.pl] [wens@csie.org: drop unsupported SPL code block and unused gpio.h header] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Tom Cubie <Mr.hipboi@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sun6i: Add support for the power reset control module found on the A31Oliver Schinagl2014-10-24-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31 has a new module called PRCM, or Power, Reset Control Module. This module controls clocks and resets for RTC block modules, and also PLL biasing in the main clock module. This patch adds the register definitions, and also enables the clocks and resets for the RTC block PIO (pin controller) and P2WI (push-pull 2 wire interface) which is used to talk to the PMIC. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: spacing fixes reported by checkpatch.pl] [wens@csie.org: Use setbits helper in PRCM init function] [wens@csie.org: rephrase commit message to explain what the hardware supports and what we actually enable] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sun6i: Add base address for the new controllers in A31Oliver Schinagl2014-10-24-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A31 has several new and changed memory address. This patch adds them. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | | ARM: sunxi: Use macro values for setting UART GPIO pull-upsChen-Yu Tsai2014-10-24-3/+3
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have already defined macros for pull-up/down values in the GPIO header. Use them instead of magic numbers when configuring the UART pins. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-10-26-0/+14
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| * | | | ARM: rpi_b: query internal MAC address from firmwareStephen Warren2014-10-22-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The built-in SMSC 95xx chip doesn't know its own MAC address. Instead, we must query it from the VC firmware; it's probably encoded in fuses on the BCM2835. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | | | Merge git://git.denx.de/u-boot-dmTom Rini2014-10-26-131/+230
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a trivial conflict over adding <dm.h> Conflicts: arch/arm/cpu/armv7/omap3/board.c Signed-off-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-11-15 02:51:08 +0000