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| * | arm: Move MAX_CPUS to KconfigYork Sun2016-10-06-5/+24
| | | | | | | | | | | | | | | | | | | | | | | | Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: Move FSL_LSCH2 FSL_LSCH3 to KconfigYork Sun2016-10-06-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: Fix Kconfig for proper display menuYork Sun2016-10-06-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | Some config options should not have prompt. They are selected by choosing target. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | armv8: fsl: Enable USB only when SYSCLK is 100 MHzSriram Dash2016-10-06-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | SYSCLK is used as a reference clock for USB. When the USB controller is used, SYSCLK must meet the additional requirement of 100 MHz. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043: Add USB node in dts for ls1043Sriram Dash2016-10-06-0/+21
| | | | | | | | | | | | | | | | | | | | | Add the USB node for LS1043 in dts. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539Hou Zhiqiang2016-10-06-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * | ARMv7: LS102xA: Move two macros from header files to KconfigHongbo Zhang2016-10-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following commits 217f92b and 1544698, these two config CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig, for correctly select ARMV7_PSCI. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Fix "cpu status" commandYork Sun2016-10-06-4/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * | armv8/fsl-layerscape: print SoC revsion numberWenbin Song2016-10-06-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv7: LS1021a: enable i-cache in start.SXiaoliang Yang2016-10-06-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First stage of u-boot can run faster after that. There is a description about skip lowlevel init in board/freescale/ls1021atwr/README. Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch2: enable snoopable sata read and writeTang Yuantian2016-10-06-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch2: adjust sata parameterTang Yuantian2016-10-06-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | common/Kconfig: Add DISPLAY_CPUINFOLokesh Vutla2016-10-12-1/+0
| |/ |/| | | | | | | | | | | | | Create a Kconfig entry for DISPLAY_CPUINFO and make it be the default in certain architectures. Migrate all config files. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-08-64/+5482
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| * | ARM: vf610: use strcpy for soc environment variableStefan Agner2016-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To create the soc environment variable we concatenate two strings on the stack. So far, strcat has been used for the first string as well as for the second string. Since the variable on the stack is not initialized, the first strcat may not start using the first entry in the character array. This then could lead to an buffer overflow on the stack. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * | arm: dts: imx7: add Ricoh RN5T567 PMIC nodeStefan Agner2016-10-07-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add device tree node for Ricoh RN5T567. Currently we do not need the individual DC/DC converters or LDO's (and they are also not yet supported by the driver). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device treeStefan Agner2016-10-07-0/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add base device for NXP i.MX 7Solo/7Dual. The two SoC are very similar and hence can share the same device tree for boot loaders purpose. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: dts: imx7: add pinctrl definesStefan Agner2016-10-07-0/+1151
| | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl defines for NXP i.MX 7Solo/7Dual SoC. The pinctrl format is compatible to the Linux kernel, hence this file is a simple copy from the Linux kernel (commit 97f5c1817b7e). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | pcm052: add new BK4r1 target based on PCM052 SoMAlbert ARIBAUD \(3ADEV\)2016-10-06-2/+57
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | tools: mkimage: add support for Vybrid image formatAlbert ARIBAUD \(3ADEV\)2016-10-06-0/+8
| | | | | | | | | | | | | | | | | | | | | This format can be flashed directly at address 0 of the NAND FLASH, as it contains all necessary headers. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | imx: imx6ul: disable POR_B internal pull upPeng Fan2016-10-04-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From TO1.1, SNVS adds internal pull up control for POR_B, the register filed is GPBIT[1:0], after system boot up, it can be set to 2b'01 to disable internal pull up. It can save about 30uA power in SNVS mode. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx-common: enlarge mux width to 4Peng Fan2016-10-04-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | For i.MX6, the mux width is 4, not 3. So enlarge the width. IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: fix USB bmode to use reserved valueStefan Agner2016-10-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the bmode "usb" uses BOOT_CFG1 to 0x01, -which means BOOT_CFG1[7:4] is set to b0000. According to Table 8-7 Boot Device Selection this is NOR/OneNAND and not Reserved. Use 0x10 which leads to b0001, which is a Reserved boot device. With that the SoC reliably falls back to the serial loader. Cc: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | arm: imx: add i.MX6ULL 14x14 EVK board supportPeng Fan2016-10-04-0/+536
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6ULL EVK board support: Add device tree file, which is copied from NXP Linux. Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR. The uart iomux settings are still keeped in board file. Boot Log: U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800) CPU: Freescale i.MX6ULL rev1.0 at 396MHz CPU: Commercial temperature grade (0C to 95C) at 15C Reset cause: POR Model: Freescale i.MX6 ULL 14x14 EVK Board Board: MX6ULL 14x14 EVK DRAM: 512 MiB MMC: initialized IMX pinctrl driver FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1 is current device Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | arm: dts: add device tree for i.MX6ULLPeng Fan2016-10-04-0/+1161
| | | | | | | | | | | | | | | | | | | | | | | | Add device tree for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de>
| * | arm: dts: imx6ull: add pinctrl definesPeng Fan2016-10-04-0/+1024
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl defines for NXP i.MX 6ULL. Since i.MX6ULL reuses some definitions of i.MX6UL, also add i.MX6UL pinctrl defines from linux kernel commit (29b4817d401). Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: iomux: fix snvs usage for i.MX6ULLPeng Fan2016-10-04-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
| * | imx: imx6ull: adjust the ldo 1.2v bandgap voltagePeng Fan2016-10-04-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: Add AIPS3 initializationPeng Fan2016-10-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Since the mx6ull adds the AIPS3, so enable its initialization. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: Update memory map addressPeng Fan2016-10-04-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | Update memory map address for mx6ull. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: update clock settings and CCM register mapPeng Fan2016-10-04-29/+89
| | | | | | | | | | | | | | | | | | | | | | | | Update Clock settings and CCM register map for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: adjust POR_B setting for i.MX6ULLPeng Fan2016-10-04-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust POR_B settings on i.MX6ULL according to IC design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: misc soc updatePeng Fan2016-10-04-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update misc SOC related settings for i.MX6ULL, such as FEC mac address, cpu speed grading and mmdc channel mask clearing. Also update s_init to skip pfd reset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ul: using runtime check when configuring PMIC_STBY_REQPeng Fan2016-10-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here, because this piece code is only for i.MX6UL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: skip setting ahb clockPeng Fan2016-10-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rom already initialized clock at 396M and 132M for arm core and ahb, so skip setting them again in U-Boot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: timer: update gpt driver for i.MX6ULLPeng Fan2016-10-04-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6ULL's GPT supportting taking OSC as clock source. Add i.MX6ULL support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx-common: introduce is_mx6ullPeng Fan2016-10-04-0/+1
| | | | | | | | | | | | | | | | | | | | | Introduce is_mx6ull macro. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: add kconfig entry for MX6ULLYe Li2016-10-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL. If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: add mx6ull major cpu typePeng Fan2016-10-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX6ULL major cpu type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ull: add iomux header filePeng Fan2016-10-04-0/+1067
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add iomux header file for i.MX6ULL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | imx: iomux-v3: fix pad setup on i.MX6DQP when CONFIG_MX6QDL is definedFilip Brozovic2016-10-04-1/+1
| |/ | | | | | | | | | | | | | | The CPU detection macro is_mx6dq returns 0 on an i.MX6DQP, so we need to check for it explicitly in order to correctly initialize the pads when CONFIG_MX6QDL is defined. Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
* | ARM: AM437X: Add Silicon ID supportLokesh Vutla2016-10-08-2/+6
| | | | | | | | | | | | | | | | | | | | Add silicon ID code for AM437x silicon. This can be used to print the cpu info using CONFIG_DISPLAY_CPUINFO. Also printing "CPU :" along with cpu name in order to be consistent with other OMAP platforms. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: dts: dra72: add rev C evm supportMugunthan V N2016-10-08-661/+589
| | | | | | | | | | | | | | | | | | | | | | Add DTS support for dra72 evm Rev C which has the following changes * Two ethernet ports now instead of the single one in rev B. * DP83867 ethernet phy instead of DP838865. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: Add return value argument to longjmpAlexander Graf2016-10-08-18/+14
| | | | | | | | | | | | | | | | | | The normal longjmp command allows for a caller to pass the return value of the setjmp() invocation. This patch adds that semantic to the arm implementation of it and adjusts the efi_loader call respectively. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: keystone: rename clk_get_rate() to ks_clk_get_rate()Masahiro Yamada2016-10-08-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | The KeyStone platform has its own clk_get_rate() but its prototype is different from that of the common-clk (clk-uclass) framework. Prefix the KeyStone specific implementation with ks_ in order to avoid name-space conflict. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone: remove declaration of unused functionsMasahiro Yamada2016-10-07-2/+0
| | | | | | | | | | | | | | | | These two functions are neither defined nor referenced. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: Add register defines for am33xx ePWM registerstomas.melin@vaisala.com2016-10-06-0/+37
| | | | | | | | | | | | | | Register definitions needed for configuring the ePWM module. Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
* | ARM: OMAP5+: Override switch_to_hypervisor functionKeerthy2016-10-06-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Override the switch_to_hypervisor function to switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for HYP mode. Based on the work done by Jonathan Bergsagel jbergsagel@ti.com. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: Introduce function to switch to hypervisor modeKeerthy2016-10-06-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | omap: Set appropriate cache configuration for LPAE and non-LAPE casesKeerthy2016-10-06-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | Cache configuration methods is different for LPAE and non-LPAE cases. Hence the bits and the interpretaion is different for two cases. In case of non-LPAE mode short descriptor format is used and we need to set Cache and Buffer bits. In the case of LPAE the cache configuration happens via MAIR0 lookup. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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