diff options
| author | Peng Fan <peng.fan@nxp.com> | 2016-09-28 09:40:27 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-10-04 19:37:39 +0200 |
| commit | f15ece388f57a3b35704b5f2306ad462ccf6e2e8 (patch) | |
| tree | d9043f71c2ec4e6b60bdd15affa5ad7adff6b772 /arch | |
| parent | 2ee4065571080b96138d9630db2fdcf6990a1289 (diff) | |
| download | u-boot-imx-f15ece388f57a3b35704b5f2306ad462ccf6e2e8.zip u-boot-imx-f15ece388f57a3b35704b5f2306ad462ccf6e2e8.tar.gz u-boot-imx-f15ece388f57a3b35704b5f2306ad462ccf6e2e8.tar.bz2 | |
imx: imx6ul: disable POR_B internal pull up
>From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 09f2b02..7b53bfd 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -362,14 +362,27 @@ int arch_cpu_init(void) set_ahb_rate(132000000); } - if (is_mx6ul() && is_soc_rev(CHIP_REV_1_0) == 0) { - /* - * According to the design team's requirement on i.MX6UL, - * the PMIC_STBY_REQ PAD should be configured as open - * drain 100K (0x0000b8a0). - * Only exists on TO1.0 - */ - writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + if (is_mx6ul()) { + if (is_soc_rev(CHIP_REV_1_0) == 0) { + /* + * According to the design team's requirement on + * i.MX6UL,the PMIC_STBY_REQ PAD should be configured + * as open drain 100K (0x0000b8a0). + * Only exists on TO1.0 + */ + writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + } else { + /* + * From TO1.1, SNVS adds internal pull up control + * for POR_B, the register filed is GPBIT[1:0], + * after system boot up, it can be set to 2b'01 + * to disable internal pull up.It can save about + * 30uA power in SNVS mode. + */ + writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & + (~0x1400)) | 0x400, + MX6UL_SNVS_LP_BASE_ADDR + 0x10); + } } if (is_mx6ull()) { |