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* arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config filesDinh Nguyen2015-09-23-2/+2
| | | | | | | | | Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-09-17-67/+316
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| * x86: quark: Configure MTRR to enable cacheBin Meng2015-09-16-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Add PCIe root port IRQ routingBin Meng2015-09-16-0/+12
| | | | | | | | | | | | | | | | Now we have enabled PCIe root port on Quark SoC, add its PIRQ routing information in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Initialize thermal sensor properlyBin Meng2015-09-16-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Thermal sensor on Quark SoC needs to be properly initialized per Quark firmware writer guide, otherwise when booting Linux kernel, it triggers system shutdown because of wrong temperature in the thermal sensor is detected by the kernel driver (see below): [ 5.119819] thermal_sys: Critical temperature reached(206 C),shutting down [ 5.128997] Failed to start orderly shutdown: forcing the issue [ 5.135495] Emergency Sync complete Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Lock HMBOUND register before jumping to kernelBin Meng2015-09-16-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When Linux kernel boots, it hangs at: [ 0.829408] Intel Quark side-band driver registered This happens when Quark kernel Isolated Memory Region (IMR) driver tries to lock an IMR register to protect kernel's text and rodata sections. However in order to have IMR function correctly, HMBOUND register must be locked otherwise the system just hangs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Convert to use clrbits, setbits, clrsetbits macrosBin Meng2015-09-16-51/+21
| | | | | | | | | | | | | | Change existing codes to use clrbits, setbits, clrsetbits macros. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add clrbits, setbits, clrsetbits macros for message port accessBin Meng2015-09-16-0/+31
| | | | | | | | | | | | | | | | | | On Intel Quark, lots of registers on the message port need be programmed. Add handy clrbits, setbits, clrsetbits macros for message port access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add PCIe/USB static register programming after memory initBin Meng2015-09-16-0/+86
| | | | | | | | | | | | | | | | | | This adds static register programming for PCIe and USB after memory init as required by Quark firmware writer guide. Although not doing this did not cause any malfunction, just do it for safety. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Convert to use driver model eth on quark/galileoBin Meng2015-09-16-19/+0
| | | | | | | | | | | | | | | | Convert to use DM version of Designware ethernet driver on Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra114: Clear IDDQ when enabling PLLCThierry Reding2015-09-16-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). The Tegra114 TRM doesn't contain this information, but the programming of PLLC is the same on Tegra114 and Tegra124. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra124: Clear IDDQ when enabling PLLCThierry Reding2015-09-16-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add Tegra20 SPI device nodesMirza Krak2015-09-16-0/+57
| | | | | | | | | | | | | | Add the device tree node for the SPI controllers found on Tegra20 SOCs. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: clk_m is the architected timer source clockThierry Reding2015-09-16-10/+8
| | | | | | | | | | | | | | | | | | | | | | While clk_m and the oscillator run at the same frequencies on Tegra114 and Tegra124, clk_m is the proper source for the architected timer. On more recent Tegra generations, Tegra210 and later, both the oscillator and clk_m can run at different frequencies. clk_m will be divided down from the oscillator. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Implement clk_mThierry Reding2015-09-16-2/+31
| | | | | | | | | | | | | | | | | | | | On currently supported SoCs, clk_m always runs at the same frequency as the oscillator input. However newer SoC generations such as Tegra210 no longer have that restriction. Prepare for that by separating clk_m from the oscillator clock and allow SoC code to override the clk_m rate. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | armv8: Make COUNTER_FREQUENCY optionalThierry Reding2015-09-16-0/+2
| | | | | | | | | | | | | | | | | | | | Some platforms have the means to determine the counter frequency at runtime, so give them an opportunity to do so. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix PLLP frequency calc on T210Stephen Warren2015-09-16-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on T210 is the VCO output, and divp is not applied. pllP_out2 does have divp applied. All other pllP_outN are divided down from pllP_out0. We only support pllP_out0 in U-Boot at the time of writing. Fix clock_get_rate() to handle this special case. This corrects the returned rate for PLLP to be 408MHz rather than 204MHz. In turn, this causes high enough dividers to be calculated for the various peripheral clocks that feed off of PLLP. Without this, some peripherals failed to operate correctly. For instance, one of my SD cards worked perfectly but an older (presumably slower) card could not be read. Note that prior to commit 722e000ccd72 "Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was 816MHz since the wrong values were being extracted from the PLLP divider register. This caused overly large peripheral dividers to be calculated, which while wrong, didn't cause any correctness issues; things simply ran slower than they could. Reported-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra: Remove tegra_spl_gpio_direction_output declaration from header fileAxel Lin2015-09-16-9/+0
| | | | | | | | | | | | | | | | | | This function is deleted by commit 2fccd2d96bad "tegra: Convert tegra GPIO driver to use driver model". Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Add p2371-2180 boardStephen Warren2015-09-16-0/+70
|/ | | | | | | | | | P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and two GPIO expansion headers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: Remove unused reference to nomadikStefan Roese2015-09-15-1/+0
| | | | | | | | | Commit 0abdd9d0 "arm: Remove nhk8815 boards and nomadik arch" missed one reference to this arch. Lets remove this as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* arm: Remove unused ST-Ericsson u8500 archStefan Roese2015-09-15-1327/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This arch does not seem to be supported / used at all in the current U-Boot mainline source tree any more. So lets remove the core u8500 code and code that was only referenced by this platform. Please note that this patch also removes these config options: - CONFIG_PL011_SERIAL_RLCR - CONFIG_PL011_SERIAL_FLUSH_ON_INIT As they only seem to be referenced by u8500 based boards. Without any such board in the current code, these config option don't make sense any more. Lets remove them as well. If someone still wants to use this platform, then please send patches to re-enable support by adding at least one board that references this code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: John Rigby <john.rigby@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-09-13-1/+10
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| * arm: rmobile: Add Stout board supportVladimir Barinov2015-08-31-1/+7
| | | | | | | | | | | | | | | | | | | | Stout is an entry level development board based on R-Car H2 SoC (R8A7790) This commit supports the following peripherals: - SCIFA, I2C, Ethernet, QSPI, SDHI0/2, CPLD Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arch: rmobile: add SCIFA port base offsetsVladimir Barinov2015-08-31-0/+3
| | | | | | | | | | | | | | add SCIFA port base offsets Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | imx-common: cpu: Do not print on invalid temperatureFabio Estevam2015-09-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not very useful to have the message below on every boot (especially when we are using early silicon): U-Boot 2015.10-rc2-23945-g37cf215 (Sep 08 2015 - 14:12:14 -0300) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device , so turn the error message into debug level. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx: mx6 discard 'select CPU_V7' for different targetsPeng Fan2015-09-13-24/+0
| | | | | | | | | | | | | | | | Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6 for different targets, because ARCH_MX6 selects CPU_V7. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | imx: mx6ul: support mx6ul 9x9 evk boardPeng Fan2015-09-13-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk, the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are: 1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC. 2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk supports 512MB DDR3 3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package. This patch add the following: 1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size() 2. Introduce a macro is_mx6ul_9x9_evk using CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work, so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with mx6ul_14x14_evk. And we have no way to dymaically checking this chip is 9x9 or 14x14. 3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations. POWER related configurations also effect for mx6ul_14x14_evk. But power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk. 4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM configurations. 5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file according to board_rev and board_name. 6. Add TARGET_MX6UL_9X9_EVK Kconfig entry Boot Log: U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53) reading u-boot.img reading u-boot.img U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 41C Reset cause: POR Board: MX6UL 9x9 EVK I2C: ready DRAM: 256 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: FEC1 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | Revert "imx: mx6: ddr correct tRFC and tXS"Peng Fan2015-09-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 059323fb6a8f21637bb617919715c2427f24777c. This commit 059323fb6a8f21637bb617919715c2427f24777c use JESD79-3E which is not the newest spec. Should use JESD79-3F in which tRFC is 260ns for 4Gb chip. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
* | imx: mx7dsabresd: Add support for MX7D SABRESD boardAdrian Alonso2015-09-13-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | * Add i.MX7D SABRESD target board support with enabled modules: UART, PMIC, USB/OTG, SD, eMMC, ENET, I2C, 74LV IOX. Build target: mx7dsabresd_config Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | imx: imx7d: add imx-common cpu support for imx7dAdrian Alonso2015-09-13-5/+38
| | | | | | | | | | | | | | | | | | Add imx-common cpu support for imx7d SoC - Update reset_cause for imx7d - Enable watchdog driver built for imx7d Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | arm: imx-common: init: rework wdog settings for imx6/imx7Adrian Alonso2015-09-13-14/+22
| | | | | | | | | | | | Rework imx_set_wdog_powerdown to be reused by imx6 and imx7 Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | arm: imx-common: init: extend init_aips to support imx7Adrian Alonso2015-09-13-24/+20
| | | | | | | | | | | | | | Extend init_aips to support imx7 SoC, use is_soc_type and is_cpu_type to resolve at run time aips3 settings Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | imx: imx7d: Add SoC system supportAdrian Alonso2015-09-13-0/+292
| | | | | | | | | | | | | | | | | | Add imx7d basic SoC system support Misc arch dependent functions for system bring up Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* | imx: imx7d: clock control module supportAdrian Alonso2015-09-13-0/+2348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add Clock control module (CCM) support * iMX7D SoC introduces 3 main clock sysmtem abstraction for clock root frequency generation denominated clock slices. Core clock slice: hihg speed clock for ARM core Bus clock slice: for bus clocks IP clock slice: Peripheral clocks * At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET In u-boot, we have to: - Configure PFD3- PFD7 for freq we needed in u-boot - Set clock root for peripherals (ip channel) Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* | imx: imx7d: initial arch level supportAdrian Alonso2015-09-13-0/+4127
| | | | | | | | | | | | | | | | | | | | | | * Add system arch level header files - imx-regs.h: iMX7D SoC system architecture registers - crm_regs.h: Clock control module registers - sys_proto.h: helper callback function for SoC setup Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* | imx: system counter driver for imx7d and mx6ulAdrian Alonso2015-09-13-0/+155
| | | | | | | | | | | | | | | | | | | | Add system counter driver for imx7d and mx6ul imx7 and imx6ul supports system counter timer as well as GPT timer (arch/arm/imx-common/timer.c); The default for imx7 is systemcounter timer. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | arm: imx: imx-common: init: move arch init common setupAdrian Alonso2015-09-13-88/+108
| | | | | | | | | | | | | | | | Move common imx6 arch init setup, init.c can be extended and reused to support imx7 SoC keeping init arch common code. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | arm: imx: common rework cache settings for imx6Adrian Alonso2015-09-13-95/+104
| | | | | | | | | | | | | | Rework cache settings for imx6, move cache configuration to imx-common/cache.c so it can be reused for newer SoC Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | thermal: imx_thermal: rework driver to be reusedAdrian Alonso2015-09-13-7/+5
| | | | | | | | | | | | | | | | Rework imx_thermal driver to be used across i.MX processor that support thermal sensor Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | imx: arch-mx6: add is_soc_type helper macroAdrian Alonso2015-09-13-0/+5
| | | | | | | | | | | | Add helper macro is_soc_type to identify iMX SoC family Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* | gpio: lpc32xx: fix issues with port3 gpioSylvain Lemieux2015-09-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current simplify lpc32xx gpio driver implementation assume a maximum of 32 GPIO per port; there are a total of 22 GPI, 24 GPO and 6 GPIO to managed on port 3. Update the driver to fix the following: 1) When requesting GPI_xx and GPO_xx on port 3 (xx is the same number) the second call to "gpio_request" will return -EBUSY. 2) The status of GPO_xx pin report the status of the corresponding GPI_xx pin when using the "gpio status" command. 3) The gpio driver may setup the direction register for the wrong gpio when calling "gpio_direction_input" (GPI_xx) or "gpio_direction_output" (GPO_xx) on port 3; the call to the direction is require to use the "gpio status" command. The following change were done in the driver: 1) port3 GPI are cache in a separate 32 bits in the array. 2) port3 direction register written only for GPIO pins. 3) port3 GPO & GPIO (as output) are read using "p3_outp_state". 4) LPC32XX_GPI_P3_GRP updated to match the change. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | bitops: introduce BIT() definitionHeiko Schocher2015-09-11-17/+0
| | | | | | | | | | | | | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* | board: Add Toby-Churchill SL50 board support.Enric Balletbò i Serra2015-09-11-0/+8
| | | | | | | | | | | | | | | | | | Add support for Lightwriter SL50 series board, a small, robust and portable Voice Output Communication Aids (VOCA) designed to meet the particular and changing needs of people with speech loss resulting from a wide range of acquired, progressive and congenital conditions. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
* | arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4Stefan Roese2015-09-11-0/+35
| | | | | | | | | | | | | | | | | | | | | | This patch adds the "nandecc" command to switch between the SPEAr600 internal 1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND chips with a stronger ECC than 1-bit, as on the x600. And to dynamically switch between both ECC schemes for backwards compatibility. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
* | arm: Remove tx25 boardSimon Glass2015-09-11-6/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove palmtreo680 boardSimon Glass2015-09-11-6/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove xaeniax boardSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove vpac270_nor_128 boardSimon Glass2015-09-11-6/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove vl_ma2sc boardSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove vision2 boardSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-11-15 17:23:19 +0000