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| author | Mirza Krak <mirza.krak@hostmobility.com> | 2015-08-19 13:50:50 +0200 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-09-16 16:10:23 -0700 |
| commit | 20613c9231d53720b35ebe8ae67a9d4cf70a3620 (patch) | |
| tree | 150747a6b01651ae99c57be09db8ae777aa1537e /arch | |
| parent | f8007235a0a50cd3538b47d1fd02e96e1f64a285 (diff) | |
| download | u-boot-imx-20613c9231d53720b35ebe8ae67a9d4cf70a3620.zip u-boot-imx-20613c9231d53720b35ebe8ae67a9d4cf70a3620.tar.gz u-boot-imx-20613c9231d53720b35ebe8ae67a9d4cf70a3620.tar.bz2 | |
ARM: tegra: Add Tegra20 SPI device nodes
Add the device tree node for the SPI controllers found on Tegra20 SOCs.
Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/tegra20.dtsi | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index b8c8a92..e68d7be 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -320,6 +320,63 @@ clocks = <&tegra_car 47>, <&tegra_car 124>; }; + spi@7000d400 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d400 0x200>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d600 0x200>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000d800 0x200>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra20-slink"; + reg = <0x7000da00 0x200>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA20_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x0078>; |