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* ARM: k2g: add SD card and eMMC supportRoger Quadros2015-10-22-0/+22
| | | | | | | | Add MMC support for k2g Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
* driver: net: keystone_net: add support for rgmii phyVitaly Andrianov2015-10-22-0/+5
| | | | | | | | | In K2G, Ethernet doesn't support SGMII instead it support RGMII, adding support to the driver to connect to RGMII phy. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* driver: net: keystone_net: fix phy mode configurationMugunthan V N2015-10-22-0/+2
| | | | | | | | | | Phy mode is a board property and it can be different between multiple board and ports, so it should not be hardcoded in driver to one specific mode. So adding a field in eth_priv_t structure to pass phy mode to driver. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: update keystone nav rx queue numbersVitaly Andrianov2015-10-22-0/+5
| | | | | | | | update K2G nav rx queue number Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: Correct base addressesVitaly Andrianov2015-10-22-0/+57
| | | | | | | | Coreect base addresses for SPI, Queue Manager, Ethernet, GPIO, and MSMC segments. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: Add support for pin mux configurationVitaly Andrianov2015-10-22-0/+58
| | | | | | | Add api for configuring pin mux. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: Add ddr3 infoVitaly Andrianov2015-10-22-1/+15
| | | | | | | Add ddr3 related info Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: Add PSC infoVitaly Andrianov2015-10-22-0/+55
| | | | | | | Add psc information for k2g Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: Add clock informationVitaly Andrianov2015-10-22-2/+14
| | | | | | | | Add clock information for Galileo Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: k2g: Add pll dataVitaly Andrianov2015-10-22-0/+31
| | | | | | | Add pll data for k2g Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: Add kconfig supportLokesh Vutla2015-10-22-0/+3
| | | | | | Add Kconfig support Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2g: Add support for CPU detectionLokesh Vutla2015-10-22-0/+9
| | | | | | Adding CPU detection support for Keystone2 Galileo. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Use dtb images by defaultLokesh Vutla2015-10-22-2/+2
| | | | | | | Now that OF_CONTROL is enabled on all keystone2 platforms, build the default images with DT. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: dts: k2e: Enable OF_CONTROL and DMLokesh Vutla2015-10-22-1/+586
| | | | | | | Import k2e specific DT files from Linux Kernel and enable OF_CONTROL, DM, DM_SERIAL. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: dts: k2l: Enable OF_CONTROL and DMLokesh Vutla2015-10-22-1/+696
| | | | | | | Import k2l specific DT files from Linux Kernel and enable OF_CONTROL, DM, DM_SERIAL. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: dts: k2hk: Enable OF_CONTROL and DMLokesh Vutla2015-10-22-0/+935
| | | | | | | Import k2hk specific DT files from Linux Kernel and enable OF_CONTROL, DM, DM_SERIAL. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: dts: keystone2: Do not use LPAE addresses in U-BootLokesh Vutla2015-10-22-9/+8
| | | | | | | | Keystone dts files assumes that LPAE is enabled and top level root node uses 64bit addresses. This breaks the keystone boot with CONFIG_OF_CONTROL enabled. So do not use 64 bit addresse in U-Boot DT. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: dts: Keystone2: Import generic dt files from Linux KernelLokesh Vutla2015-10-22-0/+738
| | | | | | | Import various generic dts files from Linux kernel so that all keystone2 platforms can be DT in U-boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Fix serial port initLokesh Vutla2015-10-22-0/+2
| | | | | | | | With CONFIG_DM_SERIAL is enabled NS16550_init() cannot be called directly. Driver probe should be taking care of this. So call this function only when DM_SERIAL is not enabled. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* sandbox: Introduce dummy remoteproc nodesNishanth Menon2015-10-22-0/+13
| | | | | | | | | Introduce dummy devices for sandbox remoteproc device and enable it by default Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* omap-common: Common get_board_serial function to pass serial through ATAGPaul Kocialkowski2015-10-22-0/+19
| | | | | | | | | Since there is a common function to grab the serial number from the die id bits, it makes sense have one to parse that serial number and feed it to the serial ATAG. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common function to display die id, replacing omap3-specific versionPaul Kocialkowski2015-10-22-24/+12
| | | | | | | | | This introduces omap_die_id_display to display the full die id. There is no need to store it in an environment variable, that no boot script is using anyway. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common serial and usbethaddr functions based on die idPaul Kocialkowski2015-10-22-24/+30
| | | | | | | | | Now that we have a common prototype to grab the omap die id, functions to figure out a serial number and usb ethernet address can use it directly. Those also get an omap_die_id prefix for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap5: omap_die_id supportPaul Kocialkowski2015-10-22-0/+12
| | | | | | | | This introduces omap5 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap4: omap_die_id supportPaul Kocialkowski2015-10-22-5/+12
| | | | | | | | This introduces omap4 support for omap_die_id, which matches the common omap_die_id definition. It replaces board-specific code to grab the die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: omap_die_id supportPaul Kocialkowski2015-10-22-10/+6
| | | | | | | | This replaces the previous get_dieid definition with omap_die_id, that matches the common omap_die_id definition. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap-common: Common omap_die_id definitionPaul Kocialkowski2015-10-22-0/+7
| | | | | | | | This introduces a common definition for omap_die_id, that aims at providing a common interface for accessing omap platform's die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-10-21-352/+1191
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| * x86: Add support for Advantech SOM-6896George McCollister2015-10-21-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Advantech SOM-6896 is a Broadwell U based COM Express Compact Module Type 6. This patch adds support for it as a coreboot payload. On board SATA and SPI are functional. On board Ethernet isn't functional but since it's optional and ties up a PCIe x4 that is otherwise brought out, this isn't a concern at the moment. USB doesn't work since the xHCI driver appears to be broken. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * x86: ivybridge: Enable the MRC cacheBin Meng2015-10-21-8/+2
| | | | | | | | | | | | | | | | | | This works correctly now, so enable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Dropped malloc() and adjusted commit message: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-21-0/+3
| | | | | | | | | | | | | | | | This code takes about 450ms without the MRC cache and about 27ms with the cache. Add a debug timer so that this time can be displayed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-21-1/+1
| | | | | | | | | | | | | | | | At present a missing $ causes this code to hang when using the MRC cache/ Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Check the RTC return valueSimon Glass2015-10-21-3/+10
| | | | | | | | | | | | | | The RTC can fail, so check the return value for reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-21-8/+8
| | | | | | | | | | | | | | For consistency, use 'ret' to handle a return value. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-21-0/+7
| | | | | | | | | | | | | | Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Init the debug UART if enabledSimon Glass2015-10-21-8/+3
| | | | | | | | | | | | | | | | | | If the debug UART is enabled, get it ready for use at the earliest possible opportunity. This is not actually very early, but until we have a stack it is difficult to make it work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Pass correct cpu_index to ap_init()Bin Meng2015-10-21-2/+2
| | | | | | | | | | | | | | | | In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten by the ap_init() function address. Correct it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Enable mrc cacheBin Meng2015-10-21-0/+4
| | | | | | | | | | | | | | | | Now that we have added MRC cache on quark support codes, enable it on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Implement mrc cacheBin Meng2015-10-21-7/+64
| | | | | | | | | | | | | | | | Using existing mrccache library to implement mrc cache support for Intel Quark. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Correct two typos for MRCBin Meng2015-10-21-2/+2
| | | | | | | | | | | | | | It should be MRC, not MCR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Remove unused rw-mrc-cache properties in the link and panther dts filesBin Meng2015-10-21-5/+0
| | | | | | | | | | | | | | | | | | "type" and "wipe-value" are never used by the mrccache codes. Remove them to avoid confusion. This also removes the alignment comment in the panther dts file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Issue full system reset in reset_cpu()Bin Meng2015-10-21-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With MRC cache enabled, when typing 'reset' in the U-Boot shell, BayTrail FSP initialization hangs at "Configuring Memory Start": Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type CurrentMrcData.BootMode = 4 Taking Fastboot path! Configuring Memory Start... Changing reset_cpu() to do a full system reset fixes this issue. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-21-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Save mrc cache to spi flashBin Meng2015-10-21-0/+19
| | | | | | | | | | | | | | Save MRC cache to SPI flash in arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()Bin Meng2015-10-21-1/+35
| | | | | | | | | | | | | | | | | | | | fsp_init() call has a parameter nvs_buf which is used by FSP as the MRC cache but currently is blindly set to NULL. Retreive the MRC cache from SPI flash and pass it to fsp_init() call. After the call, save FSP produced MRC cache to SPI flash too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-21-15/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-21-108/+4
| | | | | | | | | | | | | | | | Remove the call to custom mrc cache APIs, and use the ones provided in the mrccache lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add more common routines to manipulate mrc cacheBin Meng2015-10-21-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds mrccache_reserve(), mrccache_get_region() and mrccache_save() APIs to the mrccache codes. They are ported from the ivybridge implementation, but with some changes. For example, in the mrccache_reserve(), ivybridge version only reserves the pure MRC data, which causes additional malloc() when saving the cache as the save API needs some meta data. Now we change it to save the whole MRC date plus the meta data to elinimate the need for the malloc() later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add various minor tidy-ups in mrccache codesBin Meng2015-10-21-18/+16
| | | | | | | | | | | | | | | | Fix some nits, improve some comments and reorder some codes a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Do sanity test on the cache record in mrccache_update()Bin Meng2015-10-21-1/+4
| | | | | | | | | | | | | | | | For the cache record to write in mrccache_update(), we should perform a sanity test to see if it is a valid one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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