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| * sparc: Serial baud rate register support multiple buses with different frequencyDaniel Hellstrom2015-12-03-4/+16
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: leon3: Clear GD_FLAG_SERIAL_READY flag on AMBA failureFrancois Retief2015-12-03-0/+1
| | | | | | | | | | | | | | | | Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the panic function can use DEBUG_UART driver. drivers/serial/serial.c set this flag before calling this function, preventing DEBUG_UART code from running. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Added function that checks if IRQ is on or offDaniel Hellstrom2015-12-03-0/+10
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: Remove version_string variable from start.S fileFrancois Retief2015-12-03-21/+6
| | | | | | | | | | | | | | Remove the version_string variable from start.S file. A weak variable is also set in the cmd_version.c file. No need for architecture override. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Move SYS_SPARC_NWINDOWS to KconfigFrancois Retief2015-12-03-0/+14
| | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-04-3/+18
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| * ARM: mxs: fix VDDD brownout settingMichael Heimpold2015-12-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value. Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV. Register content calculation: (1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14 Register takes only 3 bits, that is 0x4. But 0x4 * 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V. Minimum possible BO level is 1500 [mV] - 0x7 * 25 [mV] = 1315 [mV]. So lets use this value as desired BO value (which is also the same as FSL bootlets use). Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * mx6: clock: Modify GPMI clock to support mx6sxYe.Li2015-11-25-0/+12
| | | | | | | | | | | | | | On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <B37916@freescale.com>
| * iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()Otavio Salvador2015-11-25-1/+1
| | | | | | | | | | | | | | | | We should also take MX6D option in consideration when defining imx_iomux_v3_setup_pad(). Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * cgtqmx6eval: Add SPL supportOtavio Salvador2015-11-25-0/+3
| | | | | | | | | | | | | | | | | | Congatec has several MX6 boards based on quad, dual, dual-lite and solo. Add SPL support so that all the variants can be supported Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Revert "rockchip: Reconfigure the malloc based to point to system memory"Sjoerd Simons2015-12-01-7/+0
| | | | | | | | | | | | | | | | | | | | | | This patch was merged shortly before the v2015.10 as a minimal fix for booting on rockchip. Now that the patch series from Hans to do the relocation in generic code has been merged it can be dropped. This reverts commit b1f492ca9e0c090209824ff36456d4f131843190. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip KconfigAriel D'Alessandro2015-12-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is evaluated. Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h board configs are now incorrect because CONFIG_SPL_BUILD is enabled so CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE instead of SYS_MALLOC_SIMPLE. This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig option by default in rockchip-mach. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add max spl size & spl header configsJeffy Chen2015-12-01-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
* | rockchip: Add basic support for evb-rk3036 boardhuang lin2015-12-01-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
* | rockchip: rk3036: Add core Soc start-up codehuang lin2015-12-01-2/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
* | rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+1107
| | | | | | | | | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add early uart driverhuang lin2015-12-01-0/+108
| | | | | | | | | | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin2015-12-01-0/+1
| | | | | | | | | | | | | | | | rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
* | rockchip: rk3036: Add a simple syscon driverhuang lin2015-12-01-1/+22
| | | | | | | | | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add Soc reset driverhuang lin2015-12-01-0/+55
| | | | | | | | | | | | | | | | We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add header files for GRFhuang lin2015-12-01-0/+493
| | | | | | | | | | | | | | GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add clock driverhuang lin2015-12-01-0/+168
| | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: Bring in RK3036 device tree file includes and bindingshuang lin2015-12-01-0/+427
| | | | | | | | | | | | | | | | | | Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add config decide whether to build common.chuang lin2015-12-01-1/+1
| | | | | | | | | | | | | | | | some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rename board-spl.c to rk3288-board-spl.chuang lin2015-12-01-1/+1
| | | | | | | | | | | | | | | | since different rockchip soc need different spl file, so rename board-spl.c. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin2015-12-01-3/+3
| | | | | | | | | | | | | | | | | | since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add timer driverhuang lin2015-12-01-19/+73
| | | | | | | | | | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: pci: Disable PCI compatibility functions by defaultSimon Glass2015-12-01-0/+4
| | | | | | | | | | | | | | | | | | We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: tegra: pci: Convert tegra boards to driver model for PCISimon Glass2015-12-01-0/+5
| | | | | | | | | | | | | | | | | | Adjust the Tegra PCI driver to support driver model and move all boards over at the same time. This can make use of some generic driver model code, such as the range-decoding logic. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: refactor common Kconfig optionsStephen Warren2015-12-01-18/+20
| | | | | | | | | | | | | | | | | | | | | | This makes it easier to select common options in a single place, rather than having to add them separately for different SoCs or architectures. The lists of select statements are now also sorted for easy searching. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: tsc: Move tsc_timer.c to drivers/timerBin Meng2015-12-01-390/+0
| | | | | | | | | | | | | | | | To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: tsc: Remove legacy timer codesBin Meng2015-12-01-80/+0
| | | | | | | | | | | | | | | | | | | | | | Now that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver. Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option, as it is not needed with driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Convert to use driver model timerBin Meng2015-12-01-39/+32
| | | | | | | | | | | | | | Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: tsc: Add driver model timer supportBin Meng2015-12-01-0/+65
| | | | | | | | | | | | | | This adds driver model timer support to x86 tsc timer driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: tsc: Use notrace from <linux/compiler.h>Bin Meng2015-12-01-3/+3
| | | | | | | | | | | | | | | | Replace __attribute__((no_instrument_function)) with notrace from <linux/compiler.h>. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Remove MIN_PORT80_KCLOCKS_DELAYBin Meng2015-12-01-20/+0
| | | | | | | | | | | | | | | | | | | | This is not referenced anywhere. Remove it, as well as tsc_base_kclocks and tsc_prev in the global data. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Fix 'Reomve' typo: Signed-off-by: Simon Glass <sjg@chromium.org>
* | timer: sandbox: Use device tree to pass the clock frequencyBin Meng2015-12-01-0/+1
| | | | | | | | | | | | | | | | We should use device tree to pass the clock frequency of the timer instead of hardcoded in the driver codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-11-30-63/+406
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| * | arm: at91/spl: atmel_sfr: move saic redirect to separate fileWenyou Yang2015-11-30-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make saic redirect code sharing with other SoCs, move the saic redirect code from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to a separate file, mach-at91/atmel_sfr.c Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each SoC has its own value. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: at91/spl: matrix: use matrix slave id macrosWenyou Yang2015-11-30-9/+34
| | | | | | | | | | | | | | | | | | | | | | | | To make matrix initialization code sharing with others, use the matrix slave id macros, instead of hard-coding. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: at91/spl: matrix: remove security peripheral select codeWenyou Yang2015-11-30-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the security peripheral select code, keep the default value in these registers, that is, the peripheral address space is configured as "Secured" access, it is suitable for SPL. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: at91/spl: matrix: remove matrix write protection codeWenyou Yang2015-11-30-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | On processor reset, the matrix write protection is disabled, so no need to disable/enable write protection when writing the matrix registers. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: at91/spl: matrix: move matrix init to separate fileWenyou Yang2015-11-30-43/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make the matrix initialization code sharing with other SoCs, move it from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to a separate file, mach-at91/matrix.c Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: atmel: Add SAMA5D2 Xplained boardWenyou Yang2015-11-30-6/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: SD card/e.MMC/SPI flash, - Support LCD display (optional, disabled by default), - Support ethernet, - Support USB mass storage. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> [fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | gpio: atmel: Add the PIO4 driver supportWenyou Yang2015-11-30-0/+48
| | | | | | | | | | | | | | | | | | | | | The PIO4 is introduced from SAMA5D2, as a new version for Atmel PIO controller. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-11-30-88/+783
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| * | | armv8: fsl-layerscape: Fix early MMU table for nand bootYork Sun2015-11-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early MMU table doesn't enable all addresses. Unused addresses are marked as invalid, as introduced by commit 9979922. An entry was missing for NAND flash space, causing nand boot failure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
| * | | armv8: ls2085a: Add workaround of errata A009635Prabhakar Kushwaha2015-11-30-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8: fsl-layerscape: Fix "cpu release" commandYork Sun2015-11-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When one core is released, other cores may not have valid entry address. Those cores are trapped by "wfe" and wait for further instruction. When their address is set, they need to be kicked off by "sev". Signed-off-by: York Sun <yorksun@freescale.com>
| * | | armv8/layerscape: Update MMU table with execute-never bitsAlison Wang2015-11-30-31/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
generated by cgit v1.1 at 2024-10-07 18:19:33 +0000